Optical sensing device

ABSTRACT

A first integrating circuit  23  converts and outputs electric currents, which are successively input from first groups of photosensitive portions via first switches  21,  into and as a voltage. A first CDS circuit  24  outputs a voltage that is in accordance with the variation amount of the voltage from the first integrating circuit  23.  A first A/D conversion circuit  25  successively inputs the voltage from the first CDS circuit  24  and converts and outputs the voltage into and as digital values. A first digital memory  26  stores the digital values, which, among the digital values output from the first A/D conversion circuit  25,  corresponds to a first period, and the digital values corresponding likewise to a second period and outputs the stored digital values to a first difference operational circuit  27.  The first difference operational circuit  27  determines the differences between the digital values corresponding to the first period and the digital values corresponding to the second period that are output from the first digital memory  26  and outputs digital values corresponding to the differences.

TECHNICAL FIELD

The present invention relates to a photodetector for detecting atwo-dimensional position where light is incident.

BACKGROUND ART

Generally, in a known photodetector, image data obtained by imaging istaken into an image memory and then two-dimensional positions aredetected after image processing, by the use of a solid-state imagesensing device such as a MOS image sensor (see for example, PatentDocument 1).

[Patent Document 1] Japanese Published Unexamined Patent Application No.H01-167769

DISCLOSURE OF THE INVENTION

In the above-described known art, however, an image memory is requiredfor storing the obtained image data, which causes a complicatedstructure of the device. Besides, since two-dimensional positions aredetected by an operation process after storing the image data into theimage memory, a detecting process of the two-dimensional positions takestime.

The present invention has been made in view of the above points, and anobject thereof is to provide a photodetector that enables high speed andsimplification of composition to be realized in regard to atwo-dimensional position detection process.

In order to achieve the above object, the present invention provides ina photodetector, having a photosensitive region, in which pixels arearrayed two-dimensionally, and being used with a light source thatilluminates light onto an object, wherein a single pixel is arranged byadjacently positioning on the same plane a plurality of photosensitiveportions, each outputting a current that is in accordance with anintensity of light incident thereon and, in each plurality of pixelsthat are aligned in a first direction of the two-dimensional array, onephotosensitive portion among the plurality of photosensitive portionsmaking up each corresponding pixel is electrically connected to the samephotosensitive portion of each of the other corresponding pixels and, ineach plurality of pixels that are aligned in a second direction of thetwo-dimensional array, another photosensitive portion among theplurality of photosensitive portions making up each corresponding pixelis electrically connected to the same photosensitive portion of each ofthe other corresponding pixels, the photodetector comprising: a firstsignal processing circuit, detecting a luminance profile in the seconddirection based on differences between outputs, corresponding to chargesaccumulated in first groups of the photosensitive portions that areelectrically connected across the pluralities of pixels aligned in thefirst direction over a first period wherein the light is illuminatedonto the object by the light source, and outputs, corresponding tocharges accumulated in the first groups of the photosensitive portionsover a second period wherein the light is not illuminated onto theobject by the light source; and a second signal processing circuit,detecting a luminance profile in the first direction based ondifferences between outputs, corresponding to charges accumulated insecond groups of the photosensitive portions that are electricallyconnected across the pluralities of pixels aligned in the seconddirection over the first period, and outputs, corresponding to chargesaccumulated in the second groups of the photosensitive portions over thesecond period.

With the present invention's photodetector, light which is incident to asingle pixel is detected by each of the plurality of photosensitiveportions that configure the pixel, and electric current corresponding tothe light intensity sensed by each photosensitive portion is outputted.Since the first groups of the photosensitive portions are electricallyconnected across each plurality of pixels aligned in the first directionof the two-dimensional array, the electric currents from the firstgroups of the photosensitive portions are sent in the first direction.Also, since the second groups of the photosensitive portions areelectrically connected across each plurality of pixels aligned in thesecond direction of the two-dimensional array, the electric currentsfrom the second groups of the photosensitive portions are sent in thesecond direction. Since the electric currents from the second groups ofthe photosensitive portions, which are electrically connected acrosseach plurality of pixels aligned in the first direction of thetwo-dimensional array, are sent in the first direction and the electriccurrents from the second groups of the photosensitive portions, whichare electrically connected across each plurality of pixels aligned inthe second direction of the two-dimensional array, are sent in thesecond direction, a luminance profile in the first direction and aluminance profile in the second direction can be obtained independentlyof each other. As a result, the two-dimensional position of the incidentlight can be detected at high speed by an extremely simple compositionwherein a plurality of photosensitive portions are disposed in a singlepixel.

Also with the present invention, by means of the first signal processingcircuit, the luminance profile in the second direction is detected basedon differences between the outputs, corresponding to the chargesaccumulated in the first groups of the photosensitive portions over thefirst period, and the outputs, corresponding to the charges accumulatedin the first groups of the photosensitive portions over the secondperiod. Thus even if background light which is incident to thephotosensitive region, the luminance profile in the second direction canbe detected in a state in which the background light components areeliminated. Also, by means of the second signal processing circuit, theluminance profile in the first direction is detected based ondifferences between the outputs, corresponding to the chargesaccumulated in the second groups of the photosensitive portions over thefirst period, and the outputs, corresponding to the charges accumulatedin the second groups of the photosensitive portions over the secondperiod. Thus even if background light which is incident to thephotosensitive region, the luminance profile in the first direction canbe detected in a state in which the background light components areeliminated. The two-dimensional position of the incident light can thusbe detected with extremely high precision.

Preferably, the first signal processing circuit comprises: a first shiftregister for successively reading, in the second direction, the electriccurrents from the first groups of the photosensitive portions; a firstintegrating circuit, successively inputting the electric currents fromthe respective first groups of the photosensitive portions that are readsuccessively by the first shift register and converting and outputtingthe electric currents into and as a voltage; a first CDS (CorrelatedDouble Sampling) circuit, outputting a voltage corresponding to thevariation amount of the voltage from the first integrating circuit; afirst A/D conversion circuit, converting the voltage from the first CDScircuit into digital values and outputting the digital values; and afirst difference operational circuit, determining, based on the digitalvalues output from the first A/D conversion circuit, differences betweendigital values corresponding to the first period and digital valuescorresponding to the second period; and the second signal processingcircuit comprises: a second shift register for successively reading, inthe first direction, the electric currents from the second groups of thephotosensitive portions; a second integrating circuit, successivelyinputting the electric currents from the respective second groups of thephotosensitive portions that are read successively by the second shiftregister and converting and outputting the electric currents into and asa voltage; a second CDS circuit, outputting a voltage corresponding tothe variation amount of the voltage from the second integrating circuit;a second A/D conversion circuit, converting the voltage from the secondCDS circuit into digital values and outputting the digital values; and asecond difference operational circuit, determining, based on the digitalvalues output from the second A/D conversion circuit, differencesbetween digital values corresponding to the first period and digitalvalues corresponding to the second period. With such a composition, evenif the first integrating circuit and the second integrating circuitrespectively have noise fluctuations that differ according to theintegrating operation, the noise errors are eliminated by the first CDScircuit and the second CDS circuit. As a result, the luminance profilein the first direction and the luminance profile in the second directioncan be obtained at high precision. Also, since electric currents areread out successively from the first and second groups of thephotosensitive portions respectively by means of the first and secondshift registers and are then subject to A/D conversion and differencedetermination, the first and second signal processing circuits can bemade simple in composition and low in cost.

Also preferably, the first signal processing circuit further comprises:a first digital memory, disposed between the first A/D conversioncircuit and the first difference operational circuit and storing thedigital values corresponding to the first period and the digital valuescorresponding to the second period and outputting the stored digitalvalues to the first difference operational circuit; and the secondsignal processing circuit further comprises: a second digital memory,disposed between the second A/D conversion circuit and the seconddifference operational circuit and storing the digital valuescorresponding to the first period and the digital values correspondingto the second period and outputting the stored digital values to thesecond difference operational circuit. With this composition,computation of the differences in the digital values corresponding tothe first period and the digital values corresponding to the secondperiod can be performed appropriately and definitely in the first andsecond difference operational circuits.

Also preferably, the first signal processing circuit comprises: firstintegrating circuits, provided in correspondence to the first groups ofthe photosensitive portions and each converting and outputting theelectric currents from the corresponding first groups of thephotosensitive portions into and as a voltage; first CDS circuits,disposed in correspondence to the first integrating circuits and each inturn comprising a first coupling capacitance element and a firstamplifier, disposed in that order between an output terminal and aninput terminal that inputs the voltage from the corresponding firstintegrating circuit, a first integrating capacitance element, disposedin parallel between the input and the output of the first amplifier, anda first switching element, making charges of an amount corresponding tothe variation amount of the voltage be accumulated in the firstintegrating capacitance element; second CDS circuits, disposed incorrespondence to the first integrating circuits and each in turncomprising a second coupling capacitance element and a second amplifier,disposed in that order between an output terminal and an input terminalthat inputs the voltage from the corresponding first integratingcircuit, a second integrating capacitance element, having a capacitancevalue equal to the capacitance value of the first integratingcapacitance element and disposed in parallel between the input and theoutput of the second amplifier, and a second switching element, makingcharges of an amount corresponding to the variation amount of thevoltage be accumulated in the second integrating capacitance element;and first difference operational circuits, disposed in correspondence tothe first CDS circuits and the second CDS circuits and each determininga difference in the amounts of charges respectively accumulated in thefirst integrating capacitance element of the corresponding first CDScircuit and the second integrating capacitance element of thecorresponding second CDS circuit and outputting a voltage that is inaccordance with the difference; and the second signal processing circuitcomprises: second integrating circuits, provided in correspondence tothe second groups of the photosensitive portions and each converting andoutputting the electric currents from the second corresponding group ofthe photosensitive portions as a voltage; third CDS circuits, disposedin correspondence to the second integrating circuits and each in turncomprising a third coupling capacitance element and a third amplifier,disposed in that order between an output terminal and an input terminalthat inputs the voltage from the corresponding second integratingcircuit, a third integrating capacitance element, disposed in parallelbetween the input and the output of the third amplifier, and a thirdswitching element, making charges of an amount corresponding to thevariation amount of the voltage be accumulated in the third integratingcapacitance element; fourth CDS circuits, disposed in correspondence tothe second integrating circuit and each in turn comprising a fourthcoupling capacitance element and a fourth amplifier, disposed in thatorder between an output terminal and an input terminal that inputs thevoltage from the corresponding second integrating circuit, a fourthintegrating capacitance element, having a capacitance value equal to thecapacitance value of the fourth integrating capacitance element anddisposed in parallel between the input and the output of the fourthamplifier, and a fourth switching element, making charges of an amountcorresponding to the variation amount of the voltage be accumulated inthe fourth integrating capacitance element; and second differenceoperational circuits, disposed in correspondence to the third CDScircuits and the fourth CDS circuits and each determining a differencein the amounts of charges respectively accumulated in the thirdintegrating capacitance element of the corresponding third CDS circuitand the fourth integrating capacitance element of the correspondingfourth CDS circuit and outputting a voltage that is in accordance withthe difference. With such a composition, since a first differenceoperational circuit is provided in accordance with each first group ofthe photosensitive portions and a second difference operational circuitis disposed in accordance with each second group of the photosensitiveportions, the luminance profiles in the first and second directions canbe obtained at high speed. Also, even if the first integrating circuitsand the second integrating circuits respectively have noise fluctuationsthat differ according to integrating operation, the noise errors areeliminated by the first to fourth CDS circuits. Also, since charges thatare in accordance with the signal light components from the light sourceand the background light components are accumulated in the first andthird integrating capacitance elements of the first and third CDScircuits during the first period, charges that are in accordance withthe background light components are accumulated in the second and fourthintegrating capacitance elements of the second and fourth CDS circuitsduring the second period, and differences between the two are determinedby the first and second difference operational circuits, the voltagesfrom the first and second difference operational circuits willcorrespond to just the signal light components from the light source.The S/N ratio of luminance profile detection will thus be excellent evenif the intensities of the light made incident on the photosensitiveregion, in other words, the above-mentioned voltages are low in value.

Also preferably, the first signal processing circuit further comprises:first sample-and-hold circuits, provided in correspondence to the firstdifference operational circuits and each holding and then outputting thevoltage from the corresponding first difference operational circuit; anda first A/D conversion circuit, successively inputting the voltages fromthe respective first sample-and-hold circuits, converting the voltagesinto digital values, and outputting the digital values; and the secondsignal processing circuit further comprises: second sample-and-holdcircuits, provided in correspondence to the second differenceoperational circuits and each holding and then outputting the voltagefrom the corresponding second difference operational circuit; and asecond A/D conversion circuit, successively inputting the voltage fromthe respective second sample-and-hold circuits, converting the voltageinto digital values, and outputting the digital values. With thiscomposition, the luminance profiles in the first and second directionscan be output as digital values.

Also preferably, the first signal processing circuit comprises: firstcharge accumulation circuits, provided in correspondence to therespective first groups of the photosensitive portions and eachcomprising a first capacitance element and a second capacitance element,disposed in parallel between an output terminal and an input terminalthat inputs the electric currents from the corresponding first group ofthe photosensitive portions, and accumulating charges in the firstcapacitance element in accordance with the electric currentscorresponding to the charges accumulated during the first period in thecorresponding first group of the photosensitive portions andaccumulating charges in the second capacitance element in accordancewith the electric currents corresponding to the charges accumulatedduring the second period in the corresponding first group of thephotosensitive portions; and a first difference operational circuit,determining the differences between the charge amounts accumulatedrespectively in the first capacitance elements and the secondcapacitance elements of the first charge accumulation circuits andoutputting a voltage that is in accordance with the differences; and thesecond signal processing circuit comprises: second charge accumulationcircuits, provided in correspondence to the respective second groups ofthe photosensitive portions and each comprising a third capacitanceelement and a fourth capacitance element, disposed in parallel betweenan output terminal and an input terminal that inputs the electriccurrents from the corresponding second group of the photosensitiveportions, and accumulating charges in the third capacitance element inaccordance with the electric currents corresponding to the chargesaccumulated during the first period in the corresponding second group ofthe photosensitive portions and accumulating charges in the fourthcapacitance element in accordance with the electric currentscorresponding to the charges accumulated during the second period in thecorresponding second group of the photosensitive portions; and a seconddifference operational circuit, determining the differences between thecharge amounts accumulated respectively in the third capacitanceelements and the fourth capacitance elements of the second chargeaccumulation circuits and outputting a voltage that is in accordancewith the differences. With this composition, by each first chargeaccumulating circuit, charges are accumulated in the first capacitanceelement in accordance with the electric currents corresponding to thecharges accumulated in the first period in the corresponding first groupof the photosensitive portions, charges are accumulated in the secondcapacitance element in accordance with the electric currentscorresponding to the charges accumulated in the second period in thecorresponding first group of the photosensitive portions, and, by thefirst difference operational circuit, the differences, between theamounts of charges accumulated respectively in the first capacitanceelements and second capacitance elements, are determined and a voltagecorresponding to the differences is output. Also, by each second chargeaccumulating circuit, charges are accumulated in the third capacitanceelement in accordance with the electric currents corresponding to thecharges accumulated in the first period in the corresponding secondgroup of the photosensitive portions, charges are accumulated in thefourth capacitance element in accordance with the electric currentscorresponding to the charges accumulated in the second period in thecorresponding second group of the photosensitive portions, and, by thesecond difference operational circuit, the differences, between theamounts of charges accumulated respectively in the third capacitanceelements and the fourth capacitance elements, are determined and avoltage corresponding to the differences is output. The first and secondsignal processing circuits can thus be made simple in composition andlow in cost.

Also, preferably the first signal processing circuit furthermorecomprises: a first integrating circuit, successively inputting, from thefirst capacitance elements and the second capacitance elements, electriccurrents corresponding to the charges accumulated in the correspondingfirst capacitance elements and second capacitance elements andconverting the electric currents into a voltage and outputting thevoltage to the first difference operational circuit; and a first A/Dconversion circuit, successively inputting the voltage from the firstdifference operational circuit, converting the voltage into digitalvalues, and outputting the digital values; and the second signalprocessing circuit furthermore comprises: a second integrating circuit,successively inputting, from the third capacitance elements and thefourth capacitance elements, electric currents corresponding to thecharges accumulated in the corresponding third capacitance elements andfourth capacitance elements and converting the electric currents into avoltage and outputting the voltage to the second difference operationalcircuit; and a second A/D conversion circuit, successively inputting thevoltage from the second difference operational circuit, converting thevoltage into digital values, and outputting the digital values. Withthis composition, the luminance profiles in the first and seconddirections can be output as digital values.

The present invention provides in a photodetector, having aphotosensitive region, in which pixels are arrayed two-dimensionally,and being used with a light source that illuminates light onto anobject, wherein a single pixel is arranged by adjacently positioning onthe same plane a plurality of photosensitive portions, each outputting acurrent that is in accordance with an intensity of light incidentthereon and, in each plurality of pixels that are aligned in a firstdirection of the two-dimensional array, one photosensitive portion amongthe plurality of photosensitive portions making up each correspondingpixel is electrically connected to the same photosensitive portion ofeach of the other corresponding pixels and, in each plurality of pixelsthat are aligned in a second direction of the two-dimensional array,another photosensitive portion among the plurality of photosensitiveportions making up each corresponding pixel is electrically connected tothe same photosensitive portion of each of the other correspondingpixels, the photodetector comprising: first eliminating circuits, beingprovided in correspondence to the respective first groups of thephotosensitive portions, which are electrically connected across eachthe plurality of pixels aligned in the first direction, and eacheliminating a electric current, which is output from the correspondingfirst group of the photosensitive portions in a second period whereinthe light is not illuminated onto the object by the light source, from aelectric current, which is output from the corresponding first group ofthe photosensitive portions in a first period wherein the light isilluminated onto the object by the light source, and outputting theelectric current resulting from the elimination; first integratingcircuits, being provided in correspondence to the first eliminatingcircuits and each accumulating charges in accordance with the electriccurrent from the corresponding first eliminating circuit and outputtinga voltage that is in accordance with the amount of the accumulatedcharges; second eliminating circuits, being provided in correspondenceto the respective second groups of the photosensitive portions, whichare electrically connected across each the plurality of pixels alignedin the second direction, and each eliminating an electric current, whichis output from the corresponding second group of the photosensitiveportions in the second period, from an electric current, which is outputfrom the corresponding second group of the photosensitive portions inthe first period, and outputting the electric current resulting from theelimination; and second integrating circuits, being provided incorrespondence to the second eliminating circuits and each accumulatingcharges in accordance with the electric current from the correspondingsecond eliminating circuit and outputting a voltage that is inaccordance with the amount of the accumulated charges.

With the present invention's photodetector, light which is incident to asingle pixel is detected by each of the plurality of photosensitiveportions making up that pixel, and a current that is in accordance withthe light intensity is output by each photosensitive portion. Since thefirst groups of the photosensitive portions are electrically connectedacross each plurality of pixels aligned in the first direction of thetwo-dimensional array, the electric currents from the first groups ofthe photosensitive portions are sent in the first direction. Also, sincethe second groups of the photosensitive portions are electricallyconnected across each plurality of pixels aligned in the seconddirection of the two-dimensional array, the electric currents from thesecond groups of the photosensitive portions are sent in the seconddirection. Since the electric currents from the first groups of thephotosensitive portions, which are electrically connected across eachplurality of pixels aligned in the first direction of thetwo-dimensional array, are sent in the first direction and the electriccurrents from the second groups of the photosensitive portions, whichare electrically connected across each plurality of pixels aligned inthe second direction of the two-dimensional array, are sent in thesecond direction, a luminance profile in the first direction and aluminance profile in the second direction can be obtained independentlyof each other. As a result, the two-dimensional position of the incidentlight can be detected at high speed by an extremely simple compositionwherein a plurality of photosensitive portions are disposed in a singlepixel.

Also with the present invention, by means of the first eliminatingcircuits, the electric currents from the first groups of thephotosensitive portions in the second period are eliminated from theelectric currents from the first groups of the photosensitive portionsin the first period. Thus even if background light which is incident tothe photosensitive region, the luminance profile in the second directioncan be detected in a state in which the background light components areeliminated. Also, by means of the second eliminating circuits, theelectric currents from the second groups of the photosensitive portionsin the above-mentioned second period are eliminated from the electriccurrents from the second groups of the photosensitive portions in thefirst period. Thus even if background light which is incident to thephotosensitive region, the luminance profile in the first direction canbe detected in a state in which the background light components areeliminated. The two-dimensional position of the incident light can thusbe detected with extremely high precision.

Also preferably, each of the first eliminating circuit comprises: afirst MOS transistor, having a source terminal connected to thecorresponding first group of the photosensitive portions and a drainterminal that is grounded; a first capacitance element, having oneterminal connected to a gate terminal of the first MOS transistor andanother terminal that is grounded; and a first switching element, havingone terminal connected to the gate terminal of the first MOS transistorand another terminal connected to the output of the corresponding firstintegrating circuit; and each second eliminating circuit comprises: asecond MOS transistor, having a source terminal connected to thecorresponding second group of the photosensitive portions and a drainterminal that is grounded; a second capacitance element, having oneterminal connected to a gate terminal of the second MOS transistor andanother terminal that is grounded; and a second switching element,having one terminal connected to the gate terminal of the second MOStransistor and another terminal connected to the output of thecorresponding second integrating circuit. By this composition, theabove-described first and second eliminating circuits can be arrangedsimply and at low cost.

Preferably, first difference operational circuits, provided incorrespondence to the first integrating circuits and each holding, fromamong the voltages from the corresponding first integrating circuit, thevoltage corresponding to the second period and outputting a voltage thatis in accordance with the difference with respect to the voltage, which,among the voltages from the corresponding first integrating circuit,corresponds to the first period; first sample-and-hold circuits,provided in correspondence to the first difference operational circuitsand each holding and outputting the voltage from the corresponding firstdifference operational circuit; a first A/D conversion circuit,successively inputting the voltages from the respective firstsample-and-hold circuits, converting the voltages into digital values,and outputting the digital values; second difference operationalcircuits, provided in correspondence to the second integrating circuitsand each holding, from among the voltages from the corresponding secondintegrating circuit, the voltage corresponding to the second period andoutputting a voltage that is in accordance with the difference withrespect to the voltage, which, among the voltages from the correspondingsecond integrating circuit, corresponds to the first period; secondsample-and-hold circuits, provided in correspondence to the seconddifference operational circuits and each holding and then outputting thevoltage from the corresponding second difference operational circuit;and a second A/D conversion circuit, successively inputting the voltagesfrom the respective second sample-and-hold circuits, converting thevoltages into digital values, and outputting the digital values. Withthis composition, the luminance profile in the first direction and theluminance profile in the second direction can be obtained at even higherprecision. Also, the luminance profiles in the first and seconddirections can be output as digital values.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a conceptual composition diagram of a photodetector of a firstembodiment.

FIG. 2 is an enlarged plan view of the principal parts of an example ofa photosensitive region included in the photodetector of the firstembodiment.

FIG. 3 is a sectional view taken along line III-III of FIG. 2.

FIG. 4 is an enlarged plan view of the principal parts of an example ofa photosensitive region included in the photodetector of the firstembodiment.

FIG. 5 is an enlarged plan view of the principal parts of an example ofa photosensitive region included in the photodetector of the firstembodiment.

FIG. 6 is an enlarged plan view of the principal parts of an example ofa photosensitive region included in the photodetector of the firstembodiment.

FIG. 7 is an enlarged plan view of the principal parts of an example ofa photosensitive region included in the photodetector of the firstembodiment.

FIG. 8 is an enlarged plan view of the principal parts of an example ofa photosensitive region included in the photodetector of the firstembodiment.

FIG. 9 is a schematic composition diagram of a first signal processingcircuit included in the photodetector of the first embodiment.

FIG. 10 is a schematic composition diagram of a second signal processingcircuit included in the photodetector of the first embodiment.

FIG. 11 is a circuit diagram of a first integrating circuit included inthe first signal processing circuit.

FIG. 12 is a circuit diagram of a first CDS circuit included in thefirst signal processing circuit.

FIG. 13A is a graph showing the variation with time of a start signalthat is input into a first shift register.

FIG. 13B is a graph showing the variation with time of a signal that isinput into the first shift register.

FIG. 13C is a graph showing the variation with time of a signal that isinput into the first shift register.

FIG. 13D is a graph showing the variation with time of a reset signalthat is input into the first integrating circuit.

FIG. 13E is a graph showing the variation with time of a signal that isoutput from the first shift register.

FIG. 13F is a graph showing the variation with time of a signal that isoutput from the first shift register.

FIG. 13G is a graph showing the variation with time of a signal that isoutput from the first shift register.

FIG. 13H is a graph showing the variation with time of a signal that isoutput from the first shift register.

FIG. 13I is a graph showing the variation with time of a voltage that isoutput from the first integrating circuit.

FIG. 14A is a graph showing the variation with time of a start signalthat is input into a second shift register.

FIG. 14B is a graph showing the variation with time of a signal that isinput into the second shift register.

FIG. 14C is a graph showing the variation with time of a signal that isinput into the second shift register.

FIG. 14D is a graph showing the variation with time of a reset signalthat is input into a second integrating circuit.

FIG. 14E is a graph showing the variation with time of a signal that isoutput from the second shift register.

FIG. 14F is a graph showing the variation with time of a signal that isoutput from the second shift register.

FIG. 14G is a graph showing the variation with time of a signal that isoutput from the second shift register.

FIG. 14H is a graph showing the variation with time of a signal that isoutput from the second shift register.

FIG. 14I is a graph showing the variation with time of a voltage that isoutput from the second integrating circuit.

FIG. 15A is a graph showing the variation with time of a start signalthat is input into the first shift register and a first A/D conversioncircuit.

FIG. 15B is a graph showing the variation with time of a start signalthat is input into a first difference operational circuit.

FIG. 15C is a graph showing the variation with time of a control signalLED that is output from a timing control circuit.

FIG. 15D is a graph showing the variation with time of an output of thefirst A/D conversion circuit.

FIG. 15E is a graph showing the variation with time of an output of thefirst difference operational circuit.

FIG. 16A is a graph showing the variation with time of a start signalthat is input into the second shift register and a second A/D conversioncircuit.

FIG. 16B is a graph showing the variation with time of a start signalthat is input into a second difference operational circuit.

FIG. 16C is a graph showing the variation with time of a control signalLED that is output from a timing control circuit.

FIG. 16D is a graph showing the variation with time of an output of thesecond A/D conversion circuit.

FIG. 16E is a graph showing the variation with time of an output of thesecond difference operational circuit.

FIG. 17 is a schematic composition diagram of a first signal processingcircuit included in a photodetector of a second embodiment.

FIG. 18 is a schematic composition diagram of a second signal processingcircuit included in the photodetector of the second embodiment.

FIG. 19 is a circuit diagram of a first CDS circuit, a second CDScircuit, and a first difference operational circuit included in thefirst signal processing circuit.

FIG. 20 is a circuit diagram of a first sample-and-hold circuit includedin the first signal processing circuit.

FIG. 21 is a timing chart for describing the operations of the firstsignal processing circuit.

FIG. 22 is a schematic composition diagram of a first signal processingcircuit included in a photodetector of a third embodiment.

FIG. 23 is a schematic composition diagram of a second signal processingcircuit included in the photodetector of the third embodiment.

FIG. 24 is a circuit diagram of a first charge accumulation circuitincluded in the first signal processing circuit.

FIG. 25 is a circuit diagram of a first integrating circuit included inthe first signal processing circuit.

FIG. 26 is a circuit diagram of a first difference operational circuitincluded in the first signal processing circuit.

FIG. 27 is a timing chart for describing the operations of the firstsignal processing circuit.

FIG. 28 is a schematic composition diagram of a first signal processingcircuit included in a photodetector of a fourth embodiment.

FIG. 29 is a schematic composition diagram of a second signal processingcircuit included in the photodetector of the fourth embodiment.

FIG. 30 is a circuit diagram of a first integrating circuit, a firsteliminating circuit, and a first difference operational circuit includedin the first signal processing circuit.

FIG. 31 is a timing chart for describing the operations of the firstsignal processing circuit.

FIG. 32 is a conceptual composition diagram showing a modificationexample of the embodiment's photodetector.

BEST MODES FOR CARRYING OUT THE INVENTION

Photodetectors of embodiments of the present invention shall now bedescribed with reference to the drawings. In the description, the samesymbol shall be used for the same elements or elements having the samefunction and redundant description shall be omitted. In the following,each of parameters M and N shall be an integer no less than 2. Also,unless stated otherwise, parameter m shall be an arbitrary integer noless than 1 and no more than M, and parameter n shall be an arbitraryinteger no less than 1 and no more than N.

First Embodiment

FIG. 1 is a conceptual composition diagram of a photodetector of a firstembodiment. As shown in FIG. 1, photodetector 1 of the presentembodiment has a photosensitive region 10, a first signal processingcircuit 20, a second signal processing circuit 30, and a timing controlcircuit 50 and is used with a light source 3 that illuminates light ontoan object. Photodetector 1 detects incidence positions, for example, ofdirect light or reflected light of spot light that is illuminated ontothe object from a light emitting element (LED, semiconductor laser,etc.) 5 of light source 3. Light source 3 has a switch 7, which isopened and closed by a control signal from timing control circuit 50,and light emitting element 5 is lit by the closing of switch 7.

In photosensitive region 10, pixels 11 _(mn) are arrayedtwo-dimensionally in M rows and N columns. One pixel is arranged byadjacently positioning, on the same plane, a photosensitive portion 12_(mn) (first photosensitive portion) and a photosensitive portion 13_(mn) (second photosensitive portion), each outputting a current that isin accordance with the intensity of light incident thereon. Thus inphotosensitive region 10, photosensitive portions 12 _(mn) andphotosensitive portions 13 _(mn) are arrayed in a two-dimensionallymixed manner on the same plane.

Across each of the pluralities of pixels 11 ₁₁ to 11 _(1N), 11 ₂₁ to 11_(2N), . . . , 11 _(M1) to 11 _(MN), aligned in a first direction in thetwo-dimensional array, one photosensitive portion 12 _(mn) among theplurality of photosensitive portions 12 _(mn) and 13 _(mn) making upeach corresponding pixel 11 _(mn) is electrically connected to the samephotosensitive portion 12 _(mn) of each of the other correspondingpixels (that is, for example, the photosensitive portions 12 ₁₁ to 12_(1N) are electrically connected to each other). Also across each of thepluralities of pixels 11 ₁₁ to 11 _(M1), 11 ₁₂ to 11 _(M2), . . . , 11_(1N) to 11 _(MN), aligned in a second direction in the two-dimensionalarray, the other photosensitive portion 13 _(mn) among the plurality ofphotosensitive portions 12 _(mn) and 13 _(mn) making up eachcorresponding pixel 11 _(mn) is electrically connected to the samephotosensitive portion 13 _(mn) of each of the other correspondingpixels (that is, for example, the photosensitive portions 13 ₁₁ to 13_(M1) are electrically connected to each other).

The composition of photosensitive region 10 shall now be described basedon FIG. 2 and FIG. 3. FIG. 2 is an enlarged plan view of the principalparts of an example of the photosensitive region included in thephotodetector, and FIG. 3 is a sectional view taken along line III-IIIof FIG. 2. In FIG. 2, the illustration of a protective layer 48 isomitted.

Photosensitive region 10 comprises a semiconductor substrate 40, formedof a P-type (first conductive type) semiconductor, and N-type (secondconductive type) semiconductor regions 41 and 42, formed on the topsurface of semiconductor substrate 40. Photosensitive portions 12 _(mn)and 13 _(mn) are thus arranged as photodiodes comprising semiconductorsubstrate 40 and sets of second conductive type semiconductor regions 41and 42. As shown in FIG. 2, each of second conductive type semiconductorregions 41 and 42 has a substantially triangular shape as viewed fromthe light-incident direction, and in a single pixel, the two regions 41and 42 are formed with one side of each being mutually adjacent.Semiconductor substrate 40 is set to the ground potential.Photosensitive region 10 may instead comprise a semiconductor substrate,formed of an N-type semiconductor, and P-type semiconductor regions,formed on the top surface of the semiconductor substrate. As can beunderstood from FIG. 2, regions 41 (photosensitive portions 12 _(mn))and regions 42 (photosensitive portions 13 _(mn)) are alignedalternately in the first direction and the second direction. Regions 41(photosensitive portions 12 _(mn)) and regions 42 (photosensitiveportions 13 _(mn)) are also aligned alternately in a third direction anda fourth direction that intersect the first direction and the seconddirection (for example, at an angle of 45°).

A first insulating layer 43 is formed on semiconductor substrate 40 andregions 41 and 42, and via contact holes formed in this first insulatinglayer 43, first wirings 44 are electrically connected to the one regions41. Also via contact holes formed in first insulating layer 43,electrodes 45 are electrically connected to the other regions 42.

A second insulating layer 46 is formed on first insulating layer 43, andvia contact holes formed in this second insulating layer 46, secondwirings 47 are electrically connected to electrodes 45. The otherregions 42 are thus electrically connected to second wirings 47 viaelectrodes 45.

A protective layer 48 is formed on second insulating layer 46. Firstinsulating layer 43, second insulating layer 46, and protective layer 48are formed of SiO₂ or SiN, etc. First wirings 44, electrodes 45, andsecond wirings 47 are formed of Al or other metal.

Each of first wirings 44 electrically connects the regions 41 in therespective pixels 11 _(mn) across the first direction and is disposed soas to extend between pixels 11 _(mn) in the first direction. By thusconnecting the one regions 41 in the respective pixels 11 _(mn) by firstwirings 44, the photosensitive portions 12 _(mn) (for example, thephotosensitive portions 12 ₁₁ to 12 _(1N)) are electrically connected toeach other across each of the pluralities of pixels 11 ₁₁ to 11 _(1N),11 ₂₁ to 11 _(2N), . . . , 11 _(M1) to 11 _(MN) that are aligned in thefirst direction in the two-dimensional array, thus forming longphotosensitive units that extend in the first direction inphotosensitive region 10. M columns of these long photosensitive unitsthat extend in the first direction are thus formed.

Each of second wirings 47 electrically connects the other regions 42 inthe respective pixels 11 _(mn) across the second direction and isdisposed so as to extend between pixels 11 _(mn) in the seconddirection. By thus connecting the other regions 42 in the respectivepixels 11 _(mn) by second wirings 47, the photosensitive portions 13_(mn) (for example, the photosensitive portions 13 ₁₁ to 13 _(M1)) areelectrically connected to each other across each of the pluralities ofpixels 11 ₁₁ to 11 _(M1), 11 ₁₂ to 11 _(M2), . . . , 11 _(1N) to 11_(MN) that are aligned in the second direction in the two-dimensionalarray, thus forming long photosensitive units that extend in the seconddirection in photosensitive region 10. N rows of these longphotosensitive units that extend in the second direction are thusformed.

In photosensitive region 10, the above-mentioned M columns of longphotosensitive units that extend in the first direction and the N rowsof long photosensitive units that extend in the second direction areformed on the same plane.

The shapes of regions 41 and 42 are not limited to the substantiallytriangular shapes shown in FIG. 2 and may be other shapes as shown inFIG. 4 to FIG. 8.

The second conductive type semiconductor regions (photosensitiveportions) shown in FIG. 4 have rectangular shapes as viewed from thelight-incident direction, and in a single pixel, the two regions 41 and42 are formed with the long sides of each being mutually adjacent.Regions 41 (photosensitive portions 12 _(mn)) and regions 42(photosensitive portions 13 _(mn)) are aligned alternately in the seconddirection. As shown in FIG. 4, even though in each pixel, the secondconductive semiconductor regions of the first direction and the seconddirection differ in area, it is sufficient that in each direction, theareas are fixed among the pixels. That is, it is sufficient that thetotal areas of the mutually connected photosensitive regions be the samefor all wirings that extend in the same direction.

With the second conductive type semiconductor regions (photosensitiveportions) shown in FIG. 5, the one regions 41, each with a substantiallytriangular shape, are formed to be continuous in the first direction.Each of the regions 42 has a substantially triangular shape and isformed independently of the others across pixels 11 _(mn). Regions 41(photosensitive portions 12 _(mn)) and regions 42 (photosensitiveportions 13 _(mn)) are aligned alternately in the second direction.Though in the case where the regions 41 are formed to be continuous inthe first direction, the provision of first wirings 44 is notnecessarily required, since the reading speed may drop in accompanimentwith an increase in serial resistance, the respective regions 41 arepreferably connected electrically by first wirings 44.

With the second conductive type semiconductor regions (photosensitiveportions) shown in FIG. 6, each pixel comprises the four regions 41 a,41 b, 42 a, and 42 b and diagonally positioned regions are electricallyconnected as a pair by a first wiring 44 or a second wiring 47. Regions41 (photosensitive portions 12 _(mn)) and regions 42 (photosensitiveportions 13 _(mn)) are aligned alternately in the first direction andthe second direction. Regions 41 (photosensitive portions 12 _(mn)) andregions 42 (photosensitive portions 13 _(mn)) are also alignedalternately in a third direction and a fourth direction.

With the second conductive semiconductor regions (photosensitiveportions), shown in FIG. 7, two pectinate regions 41 and 42 are formedin a mutually engaged manner.

Each of the second conductive type semiconductor regions (photosensitiveportions) shown in FIG. 8 has a polygonal shape (for example, anoctagonal shape) with no less than four sides as viewed from thelight-incident direction, and in a single pixel, the regions are formedwith one side of each being mutually adjacent. In a single pixel, aregion 41 and a region 42 are positioned along a third direction thatintersects the first direction and the second direction and, as viewedfrom the light-incident direction, are arrayed in honeycomb-like manner.Regions 41 (photosensitive portions 12 _(mn)) and regions 42(photosensitive portions 13 _(mn)) are thus aligned alternately in thethird direction and a fourth direction.

The compositions of first signal processing circuit 20 and second signalprocessing circuit 30 shall now be described based on FIG. 9 and FIG.10. FIG. 9 is a schematic composition diagram of the first signalprocessing circuit, and FIG. 10 is a schematic composition diagram ofthe second signal processing circuit.

First signal processing circuit 20 detects a luminance profile in thesecond direction based on the differences between outputs, correspondingto charges accumulated in the first groups of the photosensitiveportions 12 _(mn) that are electrically connected across the pluralitiesof pixels 11 ₁₁ to 11 _(1N), 11 ₂₁ to 11 _(2N), . . . , 11 _(M1) to 11_(MN) aligned in the first direction (the M columns of longphotosensitive units that extend in the first direction and comprise thesecond conductive type semiconductor regions 41) during a first periodin which spot light is illuminated by light source 3 onto the object,and outputs, corresponding to charges accumulated in the first groups ofthe photosensitive portions 12 _(mn) during a second period in whichspot light is not illuminated by light source 3 onto the object. Asshown in FIG. 9, first signal processing circuit 20 comprises firstswitches 21, disposed in correspondence to the first groups of thephotosensitive portions 12 _(mn) that are electrically connected acrossthe pluralities of pixels 11 ₁₁ to 11 _(1N), 11 ₂₁ to 11 _(2N), . . . ,11 _(M1) to 11 _(MN) aligned in the first direction, a first shiftregister 22 for successively reading, in the second direction, theelectric currents from the first groups of the photosensitive portions12 _(mn) that are electrically connected across the pluralities ofpixels 11 ₁₁ to 11 _(1N), 11 ₂₁ to 11 _(2N), . . . , 11 _(M1) to 11_(MN) aligned in the first direction, and a first integrating circuit23, successively inputting the electric currents from the respectivefirst groups of the photosensitive portions 12 _(mn) that are readsuccessively by first shift register 22 and converting and outputtingthese electric currents as a voltage. First signal processing circuit 20also has a first CDS circuit 24, a first A/D conversion circuit 25, afirst digital memory 26, and a first difference operational circuit 27.

First switches 21 are closed successively by being controlled by signalsshift(H_(m)), which are output from first shift register 22. By closingfirst switches 21, the charges that are accumulated in the first groupsof the photosensitive portions 12 _(mn) that are electrically connectedacross the pluralities of pixels 11 ₁₁ to 11 _(1N), 11 ₂₁ to 11 _(2N), .. . , 11 _(M1) to 11 _(MN) aligned in the first direction becomeelectric currents that are output via first wirings 44 and firstswitches 21 to first integrating circuit 23. First shift register 22 iscontrolled in operation and closes first switches 21 successively inaccordance with signals Φ_(H1), Φ_(H2), and Φ_(Hst1), which are outputfrom timing control circuit 50.

As shown in FIG. 11, first integrating circuit 23 comprises an amp A₁,inputting the electric currents from the first groups of thephotosensitive portions 12 _(mn), which are electrically connectedacross the pluralities of pixels 11 ₁₁ to 11 _(1N), 11 ₂₁ to 11 _(2N), .. . , 11 _(M1) to 11 _(MN) aligned in the first direction, andamplifying the charges of the input electric currents, a capacitor C₁,having one terminal connected to the input terminal of amp A₁ and havingthe other terminal connected to the output terminal of amp A₁, and aswitch SW₁, having one terminal connected to the input terminal of ampA₁, having the other terminal connected to the output terminal of ampA₁, being put in the “ON” state when a reset signal Φ_(Hreset) (notshown), output from timing control circuit 50 is significant, and beingput in the “OFF” state when reset signal Φ_(Hreset), is non-significant.

When switch SW₁ is in the “ON” state, first integrating circuit 23discharges and initializes capacitor C₁. On the other hand, when switchSW₁ is in the “OFF” state, first integrating circuit 23 accumulates, incapacitor C₁, the charges input in the input terminal from the firstgroups of the photosensitive portions 12 _(mn) that are electricallyconnected across the pluralities of pixels 11 ₁₁ to 11 _(1N), 11 ₂₁ to11 _(2N), . . . , 11 _(M1) to 11 _(MN) aligned in the first directionand outputs, from the output terminal, a voltage that is in accordancewith the accumulated charges.

The operations of first switch 21, first shift register 22, and firstintegrating circuit 23 shall now be described based on FIG. 13A to FIG.13I. FIG. 13A to FIG. 13I are timing charts for describing theoperations of the first switch, the first shift register, and the firstintegrating circuit in the first signal processing circuit.

When start signal Φ_(Hst1) is input from timing control circuit 50 intofirst shift register 22 (see FIG. 13A), signals shift(H_(m)), eachhaving a pulse width corresponding to the period between the rising edgeof signal Φ_(H2) to the trailing edge of signal Φ_(H1), are outputsuccessively (see FIGS. 13B, 13C, and 13E to 13H). When a signalshift(H_(m)) is output from first shift register 22 to a correspondingfirst switch 21, the corresponding first switch 21 closes successivelyand the charges accumulated in the corresponding first group of thephotosensitive portions 12 _(mn) become output successively as electriccurrents to first integrating circuit 23.

Reset signal Φ_(Hreset) from timing control circuit 50 is input intofirst integrating circuit 23 (see FIG. 13D). During the period in whichreset signal Φ_(Hreset) is in the “OFF” state, the charges accumulatedin the corresponding group of the photosensitive portions 12 _(mn) areaccumulated in capacitor C₁ and a voltage, which is in accordance withthe amount of the accumulated charges, is successively output from firstintegrating circuit 23 (see FIG. 131). When reset signal Φ_(Hreset) isin the “ON” state, first integrating circuit 23 closes switch SW₁ andinitializes capacitor C₁.

Thus from first integrating circuit 23, a voltage, corresponding to thecharges accumulated in the first groups of the photosensitive portions12 _(mn) that are electrically connected across the pluralities ofpixels 11 ₁₁ to 11 _(1N), 11 ₂₁ to 11 _(2N), . . . , 11 _(M1) to 11_(MN) aligned in the first direction, is output successively as timeseries data in accordance with the corresponding first groups of thephotosensitive portions 12 _(mn). This time series data indicates theluminance profile (analog data) in the second direction.

Referring again to FIG. 9, first CDS circuit 24 outputs a voltage thatis in accordance with the variation amount of the voltage from firstintegrating circuit 23. As shown in FIG. 12, first CDS circuit 24 has aswitch SW₂₁, a coupling capacitor C₂₁, and an amp A₂, disposed in thatorder between an input terminal and an output terminal. Also, a switchSW₂₂ and an integrating capacitor C₂₂ are connected in parallel to eachother between the input and the output of amp A₂. Switches SW₂₂ and SW₂₁function as switching element for accumulating charges in integratingcapacitor C₂₂. When switch SW₂₂ is closed, first CDS circuit 24discharges and initializes integrating capacitor C₂₂. When switch SW₂₂is opened and switch SW₂₁ is closed, charges that are input from theinput terminal and via coupling capacitor C₂₁ are accumulated inintegrating capacitor C₂₂, and a voltage that is in accordance with theaccumulated charges is output from the output terminal. Switch SW₂₁opens and closes based on a CSW21 signal output from timing controlcircuit 50. Also, switch SW₂₂ opens and closes based on a Clamp 1 signaloutput from timing control circuit 50.

First A/D conversion circuit 25 successively inputs the voltage (analogvalues) from first CDS circuit 24, converts this voltage into digitalvalues, and outputs the digital values. A clock pulse signal (not shown)and a start signal Φ_(Hst1) are input from timing control circuit 50into first A/D conversion circuit 25, which operates based on thesesignals. The digital values output from first A/D conversion circuit 25become outputs that express the luminance profile (digital data) in thesecond direction.

First digital memory 26 stores digital values, which, among the digitalvalues output from first A/D conversion circuit 25, correspond to thefirst period (the values resulting from the A/D conversion of thevoltage (analog values) converted from the electric currentscorresponding to the charges accumulated in the first groups of thephotosensitive portions 12 _(mn) during the above-mentioned firstperiod), likewise stores digital values corresponding to the secondperiod (the values resulting from the A/D conversion of the voltage(analog values) converted from the electric currents corresponding tothe charges accumulated in the first groups of the photosensitiveportions 12 _(mn) during the above-mentioned second period), and outputsthe stored digital values to first difference operational circuit 27.Start signals Φ_(Hst1) and Φ_(Hst2) (not shown) are input from timingcontrol circuit 50 into first digital memory 26, which operates based onthese signals.

During the above-mentioned first period, light source 3 is lit. That is,this is the period during which switch 7 is closed based on the controlsignal from timing control circuit 50 and spot light is illuminated fromlight emitting element 5. Thus of the digital values output from firstA/D conversion circuit 25, the digital values corresponding to the firstperiod are outputs that express the luminance profile in the seconddirection that includes spot light components (signal light components)from light emitting element 5 and background light components (forexample, light from a fluorescent lamp, sun, etc.).

During the above-mentioned second period, light source 3 is not lit.That is, this is the period during which switch 7 is opened based on thecontrol signal from timing control circuit 50 and spot light is notilluminated from light emitting element 5. Thus of the digital valuesoutput from first A/D conversion circuit 25, the digital valuescorresponding to the first period are outputs that express the luminanceprofile in the second direction that contains just the background lightcomponents (for example, light from a fluorescent lamp, sun, etc.).

First difference operational circuit 27 determines the differencesbetween the digital values corresponding to the first period and thedigital values corresponding to the second period that are output fromfirst digital memory 26 and outputs digital values corresponding tothese differences. The digital values output from first differenceoperational circuit 27 are thus outputs that express the luminanceprofile in the second direction, from which the background lightcomponents have been eliminated and which contain just the spot lightcomponents.

The operations of first difference operational circuit 27 shall now bedescribed based on FIG. 15A to FIG. 15E. FIG. 15A to FIG. 15E are timingcharts for describing the operations of the first difference operationalcircuit in the first signal processing circuit. In FIG. 15D and FIG.15E, the digital outputs of the first A/D conversion circuit and thefirst difference operational circuit are shown in the form of analogoutputs for the sake of description.

When switch 7 is closed for a predetermined period during which controlsignal LED from timing control circuit 50 is “High” (see FIG. 15C), spotlight is illuminated from light emitting element 5 just for a durationcorresponding to the predetermined period. Then in synchronization withstart signal Φ_(Hst1), a voltage is output from first integratingcircuit 23 and digital values are output successively from first A/Dconversion circuit 25 as described above (see FIG. 15A and FIG. 15D).The digital values output from first A/D conversion circuit 25 arestored in first digital memory 26 according to the above-mentioneddigital values corresponding to the first period and the digital valuescorresponding to the second period. In synchronization with start signalΦ_(Hst2), output from timing control circuit 50, first differenceoperational circuit 27 reads out the digital values corresponding to thefirst period and the digital values corresponding to the second periodthat are stored in first digital memory 26, determines the differencesbetween the two, and outputs digital values that are in accordance withthe differences (see FIG. 15B and FIG. 15E).

Second signal processing circuit 30 detects a luminance profile in thefirst direction based on the differences between outputs, correspondingto charges accumulated in the second groups of the photosensitiveportions 13 _(mn) that are electrically connected across the pluralitiesof pixels 11 ₁₁ to 11 _(M1), 11 ₁₂ to 11 _(M2), . . . , 11 _(1N) to 11_(MN) aligned in the second direction (the N rows of long photosensitiveunits that extend in the second direction and comprise the secondconductive type semiconductor regions 42) during a first period in whichspot light is illuminated by light source 3 onto the object, andoutputs, corresponding to charges accumulated in the second groups ofthe photosensitive portions 13 _(mn) during a second period in whichspot light is not illuminated by light source 3 onto the object. Asshown in FIG. 10, second signal processing circuit 30 comprises secondswitches 31, disposed in correspondence to the second groups of thephotosensitive portions 13 _(mn) that are electrically connected acrossthe pluralities of pixels 11 ₁₁ to 11 _(M1), 11 ₁₂ to 11 _(M2), . . . ,11 _(1N) to 11 _(MN) aligned in the second direction, a second shiftregister 32 for successively reading, in the first direction, theelectric currents from the second groups of the photosensitive portions13 _(mn) that are electrically connected across the pluralities ofpixels 11 ₁₁ to 11 _(M1), 11 ₁₂ to 11 _(M2), . . . , 11 _(1N) to 11_(MN) aligned in the second direction, and a second integrating circuit33, successively inputting the electric currents from the respectivesecond groups of the photosensitive portions 13 _(mn) that are readsuccessively by second shift register 32 and converting and outputtingthese electric currents as a voltage. Second signal processing circuit30 also has a second CDS circuit 34, a second A/D conversion circuit 35,a second digital memory 36, and a second difference operational circuit37.

Second switches 31 are closed successively by being controlled bysignals shift(V_(n)), which are output from second shift register 32. Byclosing second switches 31, the charges that are accumulated in thesecond groups of the photosensitive portions 13 _(mn) that areelectrically connected across the pluralities of pixels 11 ₁₁ to 11_(M1), 11 ₁₂ to 11 _(M2), . . . , 11 _(1N) to 11 _(MN) aligned in thesecond direction become electric currents that are output via secondwirings 47 and second switches 31 to second integrating circuit 33.Second shift register 32 is controlled in operation and closes secondswitches 31 successively in accordance with signals Φ_(V1), Φ_(V2), andΦ_(Vst1), which are output from timing control circuit 50.

Second integrating circuit 33 has an composition equivalent to firstintegrating circuit 23 shown in FIG. 11 and comprises an amplifier,inputting the electric currents from the second groups of thephotosensitive portions 13 _(mn), which are electrically connectedacross the pluralities of pixels 11 ₁₁ to 11 _(M1), 11 ₁₂ to 11 _(M2), .. . , 11 _(1N) to 11 _(MN) aligned in the second direction, andamplifying the charges of the input electric currents, a capacitor,having one terminal connected to the input terminal of the amplifier andhaving the other terminal connected to the output terminal of theamplifier, and a switch, having one terminal connected to the inputterminal of the amp, having the other terminal connected to the outputterminal of the amplifier, being put in the “ON” state when a resetsignal Φ_(Vreset) (not shown), output from timing control circuit 50 issignificant, and being put in the “OFF” state when reset signalΦ_(Vreset), is non-significant.

When the switch is in the “ON” state, second integrating circuit 33discharges and initializes the capacitor. On the other hand, when theswitch is in the “OFF” state, second integrating circuit 33 accumulates,in the capacitor, the charges input in the input terminal from thesecond groups of the photosensitive portions 13 _(mn) that areelectrically connected across the pluralities of pixels 11 ₁₁ to 11_(M1), 11 ₁₂ to 11 _(M2), . . . , 11 _(1N) to 11 _(MN) aligned in thesecond direction and outputs, from the output terminal, a voltage thatis in accordance with the accumulated charges.

The operations of second switch 31, second shift register 32, and secondintegrating circuit 33 shall now be described based on FIG. 14A to FIG.14I. FIG. 14A to FIG. 14I are timing charts for describing theoperations of the second switch, the second shift register, and thesecond integrating circuit in the second signal processing circuit.

When start signal Φ_(Vst1) is input from timing control circuit 50 intosecond shift register 32 (see FIG. 14A), signals shift(V_(n)), eachhaving a pulse width corresponding to the period between the rising edgeof signal Φ_(V2) to the trailing edge of signal Φ_(V1), are outputsuccessively (see FIGS. 14B, 14C, and 14E to 14H). When a signalshift(V_(n)) is output from second shift register 32 to a correspondingsecond switch 31, the corresponding second switch 31 closes successivelyand the charges accumulated in the corresponding second group of thephotosensitive portions 13 _(mn) become output successively as electriccurrents to second integrating circuit 33.

Reset signal Φ_(Vreset) from timing control circuit 50 is input intosecond integrating circuit 33 (see FIG. 14E). During the period in whichreset signal Φ_(Vreset) is in the “OFF” state, the charges accumulatedin the corresponding second group of the photosensitive portions 13_(mn) are accumulated in the capacitor and a voltage, which is inaccordance with the amount of the accumulated charges, is successivelyoutput from second integrating circuit 33 (see FIG. 14I). When resetsignal Φ_(Vreset) is in the “ON” state, second integrating circuit 33closes the switch and initializes the capacitor.

Thus from second integrating circuit 33, a voltage, corresponding to thecharges (electric currents) accumulated in the second groups of thephotosensitive portions 13 _(mn) that are electrically connected acrossthe pluralities of pixels 11 ₁₁ to 11 _(M1), 11 ₁₂ to 11 _(M2), . . . ,11 _(1N) to 11 _(MN) aligned in the second direction, is outputsuccessively as time series data in accordance with the correspondingsecond groups of the photosensitive portions 13 _(mn). This time seriesdata indicates the luminance profile (analog data) in the firstdirection.

Referring again to FIG. 10, second CDS circuit 34 outputs a voltage thatis in accordance with the variation amount of the voltage from secondintegrating circuit 33. Second CDS circuit 34 has an compositionequivalent to first CDS circuit 24, shown in FIG. 12, and has a switch,a coupling capacitor, and an amplifier, disposed in that order betweenan input terminal and an output terminal. Also, a switch and anintegrating capacitor are connected in parallel to each other betweenthe input and output of the amplifier.

Second A/D conversion circuit 35 successively inputs the voltage (analogvalues) from second CDS circuit 34, converts this voltage into digitalvalues, and outputs the digital values. A clock pulse signal (not shown)and a start signal Φ_(Vst1) are input from timing control circuit 50into second A/D conversion circuit 35, which operates based on thesesignals. The digital values output from second A/D conversion circuit 35become outputs that express the luminance profile (digital data) in thefirst direction.

Second digital memory 36 stores digital values, which, among the digitalvalues output from second A/D conversion circuit 35, correspond to thefirst period (the values resulting from the A/D conversion of thevoltage (analog values) converted from the electric currentscorresponding to the charges accumulated in the second groups of thephotosensitive portions 13 _(mn) during the above-mentioned firstperiod), likewise stores digital values corresponding to the secondperiod (the values resulting from the A/D conversion of the voltage(analog values) converted from the electric currents corresponding tothe charges accumulated in the second groups of the photosensitiveportions 13 _(mn) during the above-mentioned second period), and outputsthe stored digital values to second difference operational circuit 37.Start signals Φ_(Vst1) and Φ_(Vst2) (not shown) are input from timingcontrol circuit 50 into second digital memory 36, which operates basedon these signals.

Second difference operational circuit 37 determines the differencesbetween the digital values corresponding to the first period and thedigital values corresponding to the second period that are output fromsecond digital memory 36 and outputs digital values corresponding tothese differences. The digital values output from second differenceoperational circuit 37 are thus outputs that express a luminance profilein the first direction, from which the background light components havebeen eliminated and which contain just the spot light components.

The operations of second difference operational circuit 37 shall now bedescribed based on FIG. 16A to FIG. 16E. FIG. 16A to FIG. 16E are timingcharts for describing the operations of the second differenceoperational circuit in the second signal processing circuit. In FIG. 16Dand FIG. 16E, the digital outputs of the second A/D conversion circuitand the second difference operational circuit are shown in the form ofanalog outputs for the sake of description.

When switch 7 is closed for a predetermined period during which controlsignal LED from timing control circuit 50 is “High” (see FIG. 16C), spotlight is illuminated from light emitting element 5 just during a periodcorresponding to the predetermined period. Then in synchronization withstart signal Φ_(Vst1), a voltage is output from second integratingcircuit 33 and digital values are output successively from second A/Dconversion circuit 35 as described above (see FIG. 16A and FIG. 16D).The digital values output from second A/D conversion circuit 35 arestored in second digital memory 36 according to the above-mentioneddigital value corresponding to the first period and digital valuecorresponding to the second period. In synchronization with start signalΦ_(Vst2), output from timing control circuit 50, second differenceoperational circuit 37 reads out the digital values corresponding to thefirst period and the digital values corresponding to the second periodthat are stored in second digital memory 36, determines the differencesbetween the two, and outputs digital values that are in accordance withthe differences (see FIG. 16B and FIG. 16E).

Thus with photodetector 1 of the present embodiment, light that is madeincident on a single pixel 11 _(mn) is made incident on each of theplurality of photosensitive portions 12 _(mn) and 13 _(mn) that make uppixel 11 _(mn) and currents that are in accordance with light intensityare output according to photosensitive portions 12 _(mn) and 13 _(mn).Since the photosensitive portions 12 _(mn) are electrically connectedacross each of the pluralities of pixels 11 ₁₁ to 11 _(1N), 11 ₂₁ to 11_(2N), . . . , 11 _(M1) to 11 _(MN) aligned in the first direction ofthe two-dimensional array, the electric currents from the photosensitiveportions 12 _(mn) are sent in the first direction. Also, since thephotosensitive portions 13 _(mn) are electrically connected across eachof the pluralities of pixels 11 ₁₁ to 11 _(M1), 11 ₁₂ to 11 _(M2), . . ., 11 _(1N) to 11 _(MN) aligned in the second direction of thetwo-dimensional array, the currents output from the photosensitiveportions 13 _(mn) are sent in the second direction. Since the currentsoutput from the photosensitive portions 12 _(mn) are sent in the firstdirection and the currents output from the photosensitive portions 13_(mn) are sent in the second direction, the luminance profile in thefirst direction and the luminance profile in the second direction can beobtained independently of the other. As a result, two-dimensionalposition of the incident light can be detected at high speed by anextremely simple composition of disposing the plurality ofphotosensitive portions 12 _(mn) and 13 _(mn) in a single pixel.

Also with photodetector 1 of the present embodiment, photosensitiveportions 12 _(mn) and 13 _(mn) comprise semiconductor substrate 40portions and second conductive type semiconductor regions 41 and 42, andas viewed from the light-incident direction, second conductive typesemiconductor regions 41 and 42 have substantially triangular shapes andare formed with one side of each being mutually adjacent in a singlepixel. The areas of the respective photosensitive portions 12 _(mn) and13 _(mn) (second conductive type semiconductor regions 41 and 42) canthus be restrained from becoming reduced in disposing the plurality ofphotosensitive portions 12 _(mn) and 13 _(mn) in a single pixel.

Also with photodetector 1 of the present embodiment, second conductivetype semiconductor regions 41 and 42 have substantially rectangularshapes as viewed from the light-incident direction and are formed withthe long sides of each being mutually adjacent in a single pixel. Theareas of the respective photosensitive portions 12 _(mn) and 13 _(mn)(second conductive type semiconductor regions 41 and 42) can thus berestrained from becoming reduced in disposing the plurality ofphotosensitive portions 12 _(mn) and 13 _(mn) in a single pixel.

Also with photodetector 1 of the present embodiment, second conductivetype semiconductor regions 41 and 42 have polygonal shapes with no lessthan four sides as viewed from the light-incident direction and areformed with one side of each being mutually adjacent in a single pixel.The areas of the respective photosensitive portions 12 _(mn) and 13_(mn) (second conductive type semiconductor regions 41 and 42) can thusbe restrained from becoming reduced in disposing the plurality ofphotosensitive portions 12 _(mn) and 13 _(mn) in a single pixel. Also,the peripheral length of each of the photosensitive portions 12 _(mn)and 13 _(mn) becomes reduced with respect to the area, and the darkcurrent per unit area becomes reduced. A rhomboid shape may be employedas a polygonal shape with no less than four sides.

Also with photodetector 1 of the present embodiment, second conductivetype semiconductor regions 41 and 42 are aligned along a thirddirection, which intersects the first direction and the seconddirection, in a single pixel. Thus in the first groups of thephotosensitive portions 12 _(mn) and the second groups of thephotosensitive portions 13 _(mn) , the photosensitive portions 12 mn and13 mn corresponding to each group of photosensitive portions 12 mn and13 mn are concentrated at the center of the corresponding group ofphotosensitive portions. Therefore, resolution can be improved.

Also with photodetector 1 of the present embodiment, second conductivetype semiconductor regions 41 and 42 are arrayed in honeycomb-like formas viewed from the light-incident direction. The areas of the respectivephotosensitive portions 12 _(mn) and 13 _(mn) (second conductive typesemiconductor regions 41 and 42) can thus be further restrained frombecoming reduced in disposing the plurality of photosensitive portions12 _(mn) and 13 _(mn) in a single pixel. Also, since the geometricalsymmetry is high, non-uniformity due to positional deviation of a maskused for forming second conductive type semiconductor regions 41 and 42(photosensitive portions 12 _(mn) and 13 _(mn)) can be restrained.

Also with photodetector 1 of the present embodiment, first wirings 44are disposed to extend between pixels 11 _(mn) in the first directionand second wirings 47 are disposed to extend between pixels 11 _(mn) inthe second direction. The incidence of light onto photosensitiveportions 12 _(mn) and 13 _(mn) (second conductive type semiconductorregions 41 and 42) will thus not be obstructed by the respective wirings44 and 47 and the lowering of detection sensitivity can be restrained.

Also with photodetector of the first embodiment, by means of firstsignal processing circuit 20, the luminance profile in the seconddirection is detected based on differences between the outputs,corresponding to the charges accumulated in the first groups of thephotosensitive portions 12 _(mn) over the first period, and the outputs,corresponding to the charges accumulated in the first groups of thephotosensitive portions 12 _(mn) over the second period. Thus even ifbackground light which is incident to photosensitive region 10, theluminance profile in the second direction can be detected in a state inwhich the background light components are eliminated. Also, by means ofsecond signal processing circuit 30, the luminance profile in the firstdirection is detected based on differences between the outputs,corresponding to the charges accumulated in the second groups of thephotosensitive portions 13 _(mn) over the first period, and the outputs,corresponding to the charges accumulated in the second groups of thephotosensitive portions 13 _(mn) over the second period. Thus even ifbackground light which is incident to photosensitive region 10, theluminance profile in the first direction can be detected in a state inwhich the background light components are eliminated. Thetwo-dimensional position of light made incident on photosensitive region10 can thus be detected with extremely high precision.

With photodetector 1 of the present embodiment, first signal processingcircuit 20 comprises first shift register 22, first integrating circuit23, first CDS circuit 24, first A/D conversion circuit 25, and firstdifference operational circuit 27, and second signal processing circuit30 comprises second shift register 32, second integrating circuit 33,second CDS circuit 34, second A/D conversion circuit 35, and seconddifference operational circuit 37. Thus even if first integratingcircuit 23 and second integrating circuit 33 respectively have noisefluctuations that differ according to integrating operation, the noiseerrors are eliminated by first CDS circuit 24 and second CDS circuit 34.As a result, the luminance profile in the first direction and theluminance profile in the second direction can be obtained at highprecision. Also, since electric currents are read out successively fromthe groups of the photosensitive portions 12 _(mn) and 13 _(mn)respectively by means of first and second shift registers 22 and 23 andare then subject to A/D conversion and difference determination, firstand second signal processing circuits 20 and 30 can be made simple incomposition and low in cost.

Also with photodetector of the present embodiment, first signalprocessing circuit 20 further comprises first digital memory 26,disposed between first A/D conversion circuit 25 and first differenceoperational circuit 27, and second signal processing circuit 30 furthercomprises second digital memory 36, disposed between second A/Dconversion circuit 35 and second difference operational circuit 37.Computation of the differences in the digital values corresponding tothe first period and the digital values corresponding to the secondperiod can thus be performed appropriately and definitely in first andsecond difference operational circuits 27 and 37.

Second Embodiment

A photodetector of a second embodiment shall now be described based onFIG. 17 to FIG. 22. The photodetector of the first embodiment and thephotodetector of the second embodiment differ in the compositions offirst signal processing circuit 20 and second signal processing circuit30.

As shown in FIG. 17, first signal processing circuit 20 of thephotodetector of the second embodiment comprises first integratingcircuits 23, first CDS circuits 121, second CDS circuits 122, firstdifference operational circuits 130, first sample-and-hold circuits(referred to hereinafter as “first S/H circuits”) 140, a first shiftregister 150, first switches 160, and a first A/D conversion circuit170. FIG. 17 is a schematic composition diagram of the first signalprocessing circuit.

First integrating circuits 23 are provided in correspondence to thefirst groups of the photosensitive portions 12 _(mn) and each convertsthe electric currents from a corresponding first group of thephotosensitive portions 12 _(mn) into a voltage and outputs thisvoltage.

First CDS circuits 121 are provided in correspondence to firstintegrating circuit 23 and each outputs a voltage that is incorrespondence to the variation amount of the voltage from thecorresponding first integrating circuit 23. As shown in FIG. 19, eachfirst CDS circuit 121 has a switch SW₂₁₁, a first coupling capacitorC₂₁₁, and a first amp (amplifier) A₂₁, disposed in that order between aninput terminal and an output terminal. Also, a switch SW₂₁₂ and a firstintegrating capacitor C₂₁₂ are connected in parallel to each otherbetween the input and output of amp A₂₁. Switches SW₂₁₁ and SW₂₁₂function as first switching element for accumulating charges in firstintegrating capacitor C₂₁₂. When switch SW₂₁₂ is closed, first CDScircuit 121 discharges and initializes first integrating capacitor C₂₁₂.When switch SW₂₁₂ is opened and switch SW₂₁₁ is closed, first charges,which are input from the input terminal and via first coupling capacitorC₂₁₁, are accumulated in first integrating capacitor C₂₁₂, and a voltagethat is in accordance with the accumulated charges is output from theoutput terminal. Switch SW₂₁₁ opens and closes based on a CSW211 signaloutput from timing control circuit 50. Also, switch SW₂₁₂ opens andcloses based on a Clamp 1 signal output from timing control circuit 50.

Second CDS circuits 122 are provided in correspondence to firstintegrating circuit 23 and each outputs a voltage that is incorrespondence to the variation amount of the voltage from thecorresponding first integrating circuit 23. As shown in FIG. 19, eachsecond CDS circuit 122 has a switch SW₂₂₁, a second coupling capacitorC₂₂₁, and a second amp A₂₂, disposed in that order between an inputterminal and an output terminal. Also, a switch SW₂₂₂ and a secondintegrating capacitor C₂₂₂ are connected in parallel to each otherbetween the input and output of amp A₂₂. Switches SW₂₂₁ and SW₂₂₂function as second switching element for accumulating charges in secondintegrating capacitor C₂₂₂. The capacitance value of second integratingcapacitor C₂₂₂ of second CDS circuit 122 is equal to the capacitancevalue of second integrating capacitor C₂₁₂ of first CDS circuit 121.When switch SW₂₂₂ is closed, second CDS circuit 122 discharges andinitializes second integrating capacitor C₂₂₂. When switch SW₂₂₂ isopened and switch SW₂₂₁ is closed, second charges, which are input fromthe input terminal and via second coupling capacitor C₂₂₁, areaccumulated in second integrating capacitor C₂₂₂, and a voltage that isin accordance with the accumulated charges is output from the outputterminal. Switch SW₂₂₁ opens and closes based on a CSW221 signal outputfrom timing control circuit 50. Also, switch SW₂₂₂ opens and closesbased on a Clamp 2 signal output from timing control circuit 50.

First difference operational circuits 130 are provided in correspondenceto first CDS circuits 121 and second CDS circuits 122 and eachdetermines the difference between the respective amounts of chargesaccumulated in first integrating capacitor C₂₁₂ of the correspondingfirst CDS circuit 121 and second integrating capacitor C₂₂₂ of thecorresponding second CDS circuit 121 and outputs a voltage correspondingto this difference. As shown in FIG. 19, each first differenceoperational circuit 130 has two input terminals 130 a and 130 b and asingle output terminal 130 c, first input terminal 130 a is connected tothe output terminal of first CDS circuit 121, and second input terminal130 b is connected to the output terminal of second CDS circuit 122.Each first difference operational circuit 130 is equipped with switchesSW₃₁ to SW₃₃, a capacitor C₃, and an amp A₃. Switch SW₃₁, capacitor C₃,and amp A₃ are disposed in that order between first input terminal 130 aand output terminal 130 c and switch SW₃₂, capacitor C₃, and amp A₃ aredisposed in that order between second input terminal 130 b and outputterminal 130 c. Also, the connection point of capacitor C₃ and amp A₃ isgrounded via switch SW₃₃.

By opening switch SW₃₂ and closing switch SW₃₁ for just a fixed periodwhile closing switch SW₃₃, first difference operational circuit 130inputs the voltage from first CDS circuit 121 and charges capacitor C₃with just charge Q₁. Also, by opening switch SW₃₁ and closing switchSW₃₂ for just a fixed period while opening switch SW₃₃, first differenceoperational circuit 130 inputs the voltage from second CDS circuit 122and discharges capacitor C₃ by just charge Q2. First differenceoperational circuit 130 thereby accumulates the difference betweencharge Q1 and charge Q2, that is, charge (Q1−Q2) in capacitor C₃ andoutputs a voltage that is in accordance with charge (Q1−Q2) in amp A₃.Switch SW₃₁ is opened and closed based on a Sample1 signal that isoutput from timing control circuit 50. Switch SW₃₂ is opened and closedbased on a Sample2 signal that is output from timing control circuit 50.Switch SW₃₃ is opened and closed based on a Clamp3 signal that is outputfrom timing control circuit 50.

First S/H circuits 140 are provided in correspondence to firstdifference operational circuits 130 and each holds and then outputs thevoltage from the corresponding first difference operational circuit 130.As shown in FIG. 20, each first S/H circuit 140 has a switch SW₄ and anamp A₄ disposed in that order between an input terminal and an outputterminal, and the connection point of switch SW₄ and amp A₃ is groundedvia a capacitor C₄. When switch SW₄ is closed, first S/H circuit 140stores the voltage from first difference operational circuit 130 incapacitor C₄, and even after switch SW₄ is opened, holds the voltage ofcapacitor C₄ and outputs this voltage via amp A₄. Switch SW₄ opens andcloses based on a Hold signal output from timing control circuit 50.First switches 160 are opened successively by being controlled by firstshift register 150 and successively inputs the voltages from first S/Hcircuits 140 into first A/D conversion circuit 170.

First A/D conversion circuit 170 successively inputs the voltages(analog values) from the respective first S/H circuits 140, convertsthese voltages into digital values, and outputs the digital values. Thedigital values output from first A/D conversion circuit 170 are outputsthat express the luminance profile (digital data) in the seconddirection.

As shown in FIG. 18, second signal processing circuit 30 of thephotodetector of the second embodiment comprises second integratingcircuits 33, third CDS circuits 221, fourth CDS circuits 222, seconddifference operational circuits 230, second sample-and-hold circuits(referred to hereinafter as “second S/H circuits”) 240, a second shiftregister 250, second switches 260, and a second A/D conversion circuit270. FIG. 18 is a schematic composition diagram of the second signalprocessing circuit.

Second integrating circuits 33 are provided in correspondence to thesecond groups of the photosensitive portions 13 _(mn) and each convertsthe electric currents from a corresponding second group of thephotosensitive portions 13 _(mn) into a voltage and outputs thisvoltage.

Third CDS circuits 221 are provided in correspondence to secondintegrating circuit 33 and each outputs a voltage that is incorrespondence to the variation amount of the voltage from thecorresponding second integrating circuit 33. Each third CDS circuit 221has an composition equivalent to that of first CDS circuit 121 shown inFIG. 19 and has a switch, a third coupling capacitor, and a third amp,disposed in that order between an input terminal and an output terminal.Also, a switch and a third integrating capacitor are connected inparallel to each other between the input and output of the third amp.The respective switches function as third switching element foraccumulating charges in the third integrating capacitor.

Fourth CDS circuits 222 are provided in correspondence to secondintegrating circuits 33 and each outputs a voltage that is incorrespondence to the variation amount of the voltage from thecorresponding second integrating circuit 33. Each fourth CDS circuit 222has an composition equivalent to that of second CDS circuit 122 shown inFIG. 19 and has a switch, a fourth coupling capacitor, and a fourth amp,disposed in that order between an input terminal and an output terminal.Also, a switch and a fourth integrating capacitor are connected inparallel to each other between the input and output of the fourth amp.The respective switches function as fourth switching element foraccumulating charges in the fourth integrating capacitor.

Second difference operational circuits 230 are provided incorrespondence to third CDS circuits 221 and fourth CDS circuits 222 andeach determines the difference between the respective amounts of chargesaccumulated in the third integrating capacitor of the correspondingthird CDS circuit 221 and the fourth integrating capacitor of thecorresponding fourth CDS circuit 221 and outputs a voltage correspondingto this difference. Each second difference operational circuit 230 has acomposition equivalent to that of first difference operational circuit130, shown in FIG. 19, and is equipped with switches, a capacitor, andan amp.

Second S/H circuits 240 are provided in correspondence to seconddifference operational circuits 230 and each holds and then outputs thevoltage from the corresponding second difference operational circuit230. Each second S/H circuit 240 has a composition equivalent to that offirst S/H circuit 140 shown in FIG. 20, has a switch and an amp disposedin that order between an input terminal and an output terminal, and theconnection point of the switch and the amp is grounded via a capacitor.Second switches 260 are opened successively by being controlled bysecond shift register 250 and successively inputs the voltages fromsecond S/H circuits 240 into second A/D conversion circuit 270.

Second A/D conversion circuit 270 successively inputs the voltages(analog values) from the respective second S/H circuits 240, convertsthese voltages into digital values, and outputs the digital values. Thedigital values output from second A/D conversion circuit 270 are outputsthat express the luminance profile (digital data) in the firstdirection.

The operations of first signal processing circuit 20 and second signalprocessing circuit 30 in the photodetector of the second embodimentshall now be described based on FIG. 21. FIG. 21 is a timing chart fordescribing the operations of the first signal processing circuit. By theoperations described below, background light components are eliminatedand the photodetected signals, concerning just the spot light components(signal light components) projected onto an object from light emittingelement 5, are output.

By the Reset signal becoming “High” at time t₁, switches SW₁ of firstintegrating circuits 23 close and capacitors C₁ are discharged andinitialized. Also, by the Clamp 1 signal becoming “High,” switches SW₂₁₂of first CDS circuits 121 close and the CDS operations of first CDScircuits 121 stop.

By the Reset signal becoming “Low” at time t₂, switches SW₁ of firstintegrating circuits 23 open. Then from time t₂ onwards, the chargesoutput from the corresponding first groups of the photosensitiveportions 12 _(mn) become accumulated in capacitors C₁ and the voltagesfrom the output terminals of first integrating circuits 23 increasegradually. At this time t₂, the logic of the Clamp1 signal remains at“High” and switches SW₂₁₂ of first CDS circuits 121 remain closed. Alsoat time t₂, the CSW211 signal is “Low” and switches SW₂₁₁ of first CDScircuits 121 are opened.

By the Clamp1 signal becoming “Low” at time t₃, switches SW₂₁₂ of firstCDS circuits 121 open, and by the CSW211 signal becoming “High”,switches SW₂₁₁ of first CDS circuits 121 close. Then at time t₄, afterthe elapse of a fixed time T from time t₃, the CSW211 signal becomes“Low” and switches SW₂₁₁ of first CDS circuits 121 open.

In the period from time t₂ to t₄, light emitting element 5 is made toemit light by control signal LED output from timing control circuit 50and a spot light is illuminated onto the object from light emittingelement 5. Thus both the spot light components, which are projected fromlight emitting element 5 and are reflected by the object, and thebackground light components become incident on photosensitive region 10and currents that are thereby generated are output from photosensitiveregions 10 (the first groups of the photosensitive portions 12 _(mn)).At first integrating circuits 23, which input the electric currents,charges are accumulated in capacitors C₁ and voltages, corresponding tothe amounts of the accumulated charges, are output from firstintegrating circuits 23. Also, in the period from time t₃ to t₄ (firstperiod), the voltages from the output terminals of first integratingcircuits 23 are input into first CDS circuits 121, the chargescorresponding to the variation amounts of the input voltages from timet₃ onwards are accumulated in first integrating capacitors C₂₁₂, andvoltages that are in accordance with the amounts of the accumulatedcharges are output from first CDS circuits 121. The voltages from firstCDS circuits 121 from time t₄ onwards are thus voltage values V_(n1)that correspond to the differences in the voltages from firstintegrating circuits 23 between time t₃ and time t₄, respectively, andare thus eliminated of the noise components that arise in firstintegrating circuits 23.

By the Reset signal becoming “High” at time t₄, switches SW₁ of firstintegrating circuits 23 close and capacitors C₁ are discharged andinitialized. Also, by the Clamp2 signal becoming “High,” switches SW₂₂₂of second CDS circuits 122 close and the CDS operations of second CDScircuits 122 stop.

By the Reset signal becoming “Low” at time t₅, switches SW₁ of firstintegrating circuits 23 open. Then from time t₅ onwards, the chargesoutput from the corresponding first groups of the photosensitiveportions 12 _(mn) become accumulated in capacitors C₁ and the voltagesfrom the output terminals of first integrating circuits 23 increasegradually. At this time t₅, the logic of the Clamp2 signal remains“High” and switches SW₂₂₂ of second CDS circuits 122 remain closed. Alsoat time t₅, the CSW221 signal is “Low” and switches SW₂₂₁ of second CDScircuits 122 are opened.

By the Clamp2 signal becoming “Low” at time t₆, switches SW₂₂₂ of secondCDS circuits 122 open, and by the CSW221 signal becoming high, switchesSW₂₂₁ of second CDS circuits 122 close. Then at time t₇, after theelapse of a fixed time T from time t₆, the CSW221 signal becomes “Low”and switches SW₂₂₁ of second CDS circuits 122 open.

In the period from time t₅ to t₇, spot light is not illuminated onto theobject from light emitting element 5. Thus only the background lightcomponents become incident on photosensitive region 10 and currents thatare thereby generated are output from photosensitive regions 10 (thefirst groups of the photosensitive portions 12 _(mn)). At firstintegrating circuits 23, which input the electric currents, charges areaccumulated in capacitors C₁ and voltages, corresponding to the amountsof the accumulated charges, are output from first integrating circuits23. Also, in the period from time t₆ to t₇ (second period), the voltagesfrom the output terminals of first integrating circuits 23 are inputinto second CDS circuits 122, the charges corresponding to the variationamounts of the input voltages from time t₆ onwards are accumulated insecond integrating capacitors C₂₂₂, and voltages that are in accordancewith the amounts of the accumulated charges are output from second CDScircuits 122. The voltages from second CDS circuits 122 from time t₇onwards are thus voltage values V_(n2) that correspond to thedifferences in the voltages from first integrating circuits 23 betweentime t₆ and time t₇, respectively, and are thus eliminated of the noisecomponents that arise in first integrating circuits 23.

From time t₇ onwards, the charges accumulated in first integratingcapacitors C₂₁₂ of first CDS circuits 121 correspond to the sum of thespot light components and the background light components, and thecharges accumulated in second integrating capacitors C₂₂₂ of second CDScircuits 122 correspond to just the background light components. Also,the period from time t₃ to t₄ (first period) and the period from time t₆to t₇ (second period) are of mutually equal duration T and since firstintegrating capacitors C₂₁₂ of first CDS circuits 121 and secondintegrating capacitors C₂₂₂ of second CDS circuits 122 are mutuallyequal in capacitance, voltage values V_(n1) correspond to the sum of thespot light components and the background light components and voltagevalues V_(n2) correspond to just the background light components.Voltage differences ΔV_(n)=(V_(n1)−V_(n2)) thus correspond to just thespot light components. Thus from time t₈ onwards, these voltagedifferences ΔV_(n) are determined first difference operational circuits130 as follows.

From time t₇ onwards (third period), the Reset signal is “High” andswitches SW₁ of first integrating circuits 23 are thus closed andcapacitors C₁ are discharged and maintained in the initialized states.The Clamp1 signal is “Low” and switches SW₂₁₂ of first CDS circuits 121remain open. Also, the Clamp2 signal is “Low” and switches SW₂₂₂ ofsecond CDS circuits 122 remain open.

In the period from time t₈ to t₉ within the third period from time t₇onwards, the Sample1 signal is “High” and switches SW₃₁ of firstdifference operational circuits 130 are thus closed. At this time, theSample2 signal is “Low” so that switches SW₃₂ of first differenceoperational circuits 130 are opened, and the Clamp3 signal is “High” sothat switches SW₃₃ of first difference operational circuits 130 areclosed. In this period, voltage values V_(n1), output from the outputterminals of first CDS circuit 121 are input into capacitors C₃ viaswitches SW₃₁ of first difference operational circuits 130 and voltagevalues V_(n1) are held by capacitors C₃.

In the period from time t₁₀ to t₁₁ within the third period from time t₇onwards, the Sample2 signal is “High” and switches SW₃₂ of firstdifference operational circuits 130 are thus closed. At this time, theSample1 signal is “Low” so that switches SW₃₁ of first differenceoperational circuits 130 are opened, and the Clamp3 signal is “Low” sothat switches SW₃₃ of first difference operational circuits 130 areopened. In this period, voltage values V_(n2), output from the outputterminals of second CDS circuit 122 are input into capacitors C₃ viaswitches SW₃₂ of first difference operational circuits 130. At thistime, since switches SW₃₃ of first difference operational circuits 130are opened, differences ΔV_(n) between voltage values V_(n1) and voltagevalues V_(n2) are held in capacitors C₃ of first difference operationalcircuits 130. These voltage values ΔV_(n) correspond to just the spotlight components.

Then when the Hold signal becomes “High” at time t₁₀ and switches SW₄ offirst S/H circuits 140 close, voltage values ΔV_(n), which are held incapacitors C₃ of first difference operational circuits 130 become heldby capacitors C₄ of first S/H circuits 140 via amps A₃ of firstdifference operational circuits 130 and switches SW₄ of first S/Hcircuits 140. Even after the Hold signal becomes Low at time t₁₁ andswitches SW₄ open, voltage values ΔV_(n) are held in capacitors C₄ offirst S/H circuits 140 and are output as voltages V_(n3) from amps A₄.Voltages V_(n3) from the respective first S/H circuits 140 aresuccessively input into first A/D conversion circuit 170, converted intodigital values, and output from first A/D conversion circuit 170 asdescribed above.

Second integrating circuits 33, third CDS circuits 221, fourth CDScircuits 222, second difference operational circuits 230, and second S/Hcircuits 240, included in second signal processing circuit 30 performoperations equivalent to those (see FIG. 21) of first integratingcircuits 23, first CDS circuits 121, second CDS circuits 122, firstdifference operational circuits 130, and first S/H circuits 140,included in first signal processing circuit 20, and voltages havingvoltage values corresponding to just the spot light component are thusoutput from second S/H circuits 240. The voltages from the respectivesecond S/H circuits 240 are successively input into second A/Dconversion circuit 270, converted into digital values, and output fromsecond A/D conversion circuit 170 as described above.

Thus even with the photodetector of the second embodiment, even whenbackground light is made incident on photosensitive region 10, theluminance profiles in the first and second directions can be detected instates in which the background light components are eliminated. As aresult, the two-dimensional position of the light made incident onphotosensitive region 10 can be detected at extremely high precision.

Also with the photodetector of the second embodiment, first signalprocessing circuit 20 includes first integrating circuits 23, first CDScircuits 121, second CDS circuits 122, and first difference operationalcircuits 130, and second signal processing circuit 30 includes secondintegrating circuits 33, third CDS circuits 221, fourth CDS circuits222, and second difference operational circuits 130. Since a firstdifference operational circuit 130 is thus provided for each first groupof the photosensitive portions 12 _(mn) and a second differenceoperational circuit 230 is provided for each second group of thephotosensitive portions 13 _(mn), the luminance profiles in the firstand second directions can be obtained at high speed. Also, even if therespective first integrating circuits 23 and second integrating circuit33 have noise fluctuations that differ according to integratingoperation, the noise errors are resolved by first to fourth CDS circuits121, 122, 221, and 222, respectively. Also, since charges, correspondingto the spot light components (signal light components) from light source3 and the background light components, are accumulated in first andthird integrating capacitors C₂₁₂ of first and third CDS circuits 121and 221 in the first period, charges, corresponding to the backgroundlight components, are accumulated in second and fourth integratingcapacitors C₂₂₂ of second and fourth CDS circuits 122 and 222 in thesecond period, and the differences between these charges are determinedby first and second difference operational circuits 130 and 230, thevoltages from first and second difference operational circuits 130 and230 correspond to just the spot light components from light source 3.Thus even when the intensity of the light made incident onphotosensitive region 10 is low, that is, even if the above-mentionedvoltages are small, the S/N ratio of luminance profile detection will beexcellent.

Also, with the photodetector of the second embodiment, first signalprocessing circuit 20 further comprises first S/H circuits 140 and firstA/D conversion circuit 170, and second signal processing circuit 30further comprises second S/H circuits 240 and second A/D conversioncircuits 270. The luminance profiles in the first and second directionscan thereby be output as digital values.

Third Embodiment

A photodetector of a third embodiment shall now be described based onFIG. 22 to FIG. 27. The photodetector of the first embodiment and thephotodetector of the third embodiment differ in the compositions offirst signal processing circuit 20 and second signal processing circuit30.

As shown in FIG. 22, first signal processing circuit 20 of thephotodetector of the third embodiment comprises first chargeaccumulation circuits 310, a first shift register 320, a firstintegrating circuit 330, a first difference operational circuit 340, anda first A/D conversion circuit 170. FIG. 22 is a general compositiondiagram of the first signal processing circuit.

First charge accumulation circuits 310 are provided in correspondence tothe first groups of the photosensitive portions 12 _(mn) and each has afirst capacitor C_(41A) and a second capacitor C_(41B), disposed inparallel between an output terminal 310B and an input terminal 310A,inputting electric currents from the corresponding first group of thephotosensitive portions 12 _(mn), and accumulates charges, which are inaccordance with electric currents corresponding to the chargesaccumulated in the corresponding first group of the photosensitiveportions 12 _(mn) over the above-mentioned first period, in firstcapacitor C_(41A), and accumulates charges, which are in accordance withelectric currents corresponding to the charges accumulated in thecorresponding first group of the photosensitive portions 12 _(mn) overthe above-mentioned second period, in second capacitor C_(41B). As shownin FIG. 24, each first charge accumulation circuit 310 has switchesSW_(41A), SW_(42A), SW_(41B), and SW_(42B). The pair of switch SW_(41A)and switch SW_(42A), which are connected to each other in cascade, andthe pair of switch SW_(41B) and switch SW_(42B), which are connected toeach other in cascade, are connected in parallel between input terminal310A and output terminal 310B. The connection point of switch SW_(41A)and switch SW_(42A), is grounded via first capacitor C_(41A). Theconnection point of switch SW_(41B) and switch SW_(42B) is grounded viasecond capacitor C_(41B). Also, the connection point of input terminal310A and switches SW_(41A) and SW_(41B) is connected to a firstreference potential V_(ref1) via a switch SW₄₃.

In the state in which switch SW₄₃ is opened, each first chargeaccumulation circuit 310 accumulates charges in first capacitor C_(41A)while switch SW_(41A) is closed and switches SW_(42A), SW_(41B), andSW_(42B) are opened and accumulates charges in second capacitor C_(41B)while switch SW_(41B) is closed and switches SW_(41A), SW_(42A), andSW_(42B) are opened. Switches SW_(41A), SW_(41B), and SW₄₃ are openedand closed based on control signals A, B, and R output from timingcontrol circuit 50. Switches SW_(42A) and SW_(42B) are controlled andsuccessively closed by signals shift(H_(mA)) and shift(H_(mB)), whichare output from first shift register 320. By closing switch SW_(42A),the charges accumulated in first capacitor C_(41A) become a current thatis output to first integrating circuit 330. Also, by closing switchSW_(42B), the charges accumulated in second capacitor C_(41B) become acurrent that is output to first integrating circuit 330. First shiftregister 320 is controlled in its operation by a signal output fromtiming control circuit 50 and successively closes switches SW_(42A) andSW_(42B).

First integrating circuit 330 successively inputs, from first capacitorsC_(41A) and second capacitors C_(41B), electric currents correspondingto the charges accumulated in first capacitors C_(41A) and secondcapacitors C_(41B), converts these electric currents into a voltage, andoutputs the voltage to first difference operational circuit 340. Asshown in FIG. 25, first integrating circuit 330 has an amp A₄₁, anintegrating capacitors C₄₂, and a switch SW₄₄ connected in parallel toeach other between an input terminal and an output terminal. Amp A₄₁ hasits inverted input terminal connected to output terminals 310B of firstcharge accumulation circuits 310, has its non-inverted input terminalset at first reference potential V_(ref1), and has its output terminalconnected to first difference operational circuit 340. Integratingcapacitors C₄₂ and switch SW₄₄ are disposed between the inverted inputterminal and the output terminal of amp A₄₁. When switch SW₄₄ is closed,first integrating circuit 330 discharges and initializes integratingcapacitors C₄₂. Meanwhile, when switch SW₄₄ is opened, first integratingcircuit 330 accumulates the charges, input into the input terminal, inintegrating capacitor C₄₂ and outputs a voltage of a value that is inaccordance with the amount of accumulated charge from the outputterminal.

First difference operational circuit 340 determines the differences ofthe amounts of the charges accumulated respectively in first capacitorsC_(41A) and second capacitors C_(41B) of first charge accumulationcircuits 310 and outputs a voltage that is in accordance with thedifferences. As shown in FIG. 26, first difference operational circuit340 has a capacitor C₄₃ and an amp A₄₂ disposed in that order between aninput terminal and an output terminal and has a switch SW₄₅ and acapacitor C₄₄ connected in parallel to each other between the input andoutput of amp A₄₂. Amp A₄₂ has its inverted input terminal connected tothe output terminal of first integrating circuit 330 and has itsnon-inverted input terminal set at a second reference potentialV_(ref2). The output terminal of first difference operational circuit340 is connected to an input terminal of first A/D conversion circuit170. First difference operational circuit 340 charges capacitor C₄₃ withjust charge Q1 from first integrating circuit 330 when switch SW₄₅ isclosed, and discharges capacitor C₄₄ by just charge Q2 that flows in viacapacitor C₄₃ from first integrating circuit 330 when switch SW₄₅ isopened. The difference between charge Q1 and charge Q2, that is, charge(Q1−Q2) is thus accumulated in capacitor C₄₄ and a voltage that is inaccordance with the accumulated charge (Q1−Q2) is output from amp A₄₂.Switch SW₄₅ is opened and closed based on a Clamp signal output fromtiming control circuit 50.

First A/D conversion circuit 170 successively inputs the voltages(analog values) from first difference operational circuit 340, convertsthese voltages into digital values, and outputs these digital values.The digital values output from first A/D conversion circuit 170 areoutputs that express the luminance profile (digital data) in the seconddirection.

As shown in FIG. 23, second signal processing circuit 30 of thephotodetector of the third embodiment comprises second chargeaccumulation circuits 410, a second shift register 420, a secondintegrating circuit 430, a second difference operational circuit 440,and a second A/D conversion circuit 270. FIG. 23 is a generalcomposition diagram of the second signal processing circuit.

Second charge accumulation circuits 410 are provided in correspondenceto the second groups of the photosensitive portions 13 _(mn) and eachhas a third capacitor and a fourth capacitor, disposed in parallelbetween an output terminal and an input terminal that inputs electriccurrents from the corresponding second group of the photosensitiveportions 13 _(mn), and accumulates charges, which are in accordance withelectric currents corresponding to the charges accumulated in thecorresponding second group of the photosensitive portions 13 _(mn) overthe above-mentioned first period, in the third capacitor, andaccumulates charges, which are in accordance with electric currentscorresponding to the charges accumulated in the corresponding group ofphotosensitive portions 13 _(mn) over the above-mentioned second period,in the fourth capacitor. Each second charge accumulation circuit 410 hasa composition equivalent to that of first charge accumulation circuit310 shown in FIG. 24 and comprises the above-mentioned third capacitor,fourth capacitor, and five switches. As with switches SW_(41A),SW_(41B), and SW₄₃, the three switches, disposed between the inputterminal and the third and fourth capacitors, open and close based oncontrol signals A, B, and R output from timing control circuit 50. Aswith switch SW_(42A) and SW_(42B), the two switches, disposed betweenthe output terminal and the third and fourth capacitors, are controlledand successively closed by signals shift(V_(nA)) and shift(V_(nB)),which are output from second shift register 420. As with first shiftregister 320, second shift register 420 is controlled in its operationby a signal output from timing control circuit 50 and successivelycloses the respective switches mentioned above.

Second integrating circuit 430 successively inputs, from the thirdcapacitors and the fourth capacitors, electric currents corresponding tothe charges accumulated in the third capacitors and the fourthcapacitors, converts these electric currents into a voltage, and outputsthe voltage to second difference operational circuit 440. Secondintegrating circuit 430 has a composition equivalent to that of firstintegrating circuit 330 shown in FIG. 25 and has an amp, an integratingcapacitor, and a switch connected in parallel to each other between aninput terminal and an output terminal. When the switch is closed, secondintegrating circuit 430 discharges and initializes the integratingcapacitor. Meanwhile, when the switch is opened, second integratingcircuit 430 accumulates the charges, input into the input terminal, inthe integrating capacitor and outputs, from the output terminal, avoltage of a value that is in accordance with the amount of accumulatedcharge.

Second difference operational circuit 440 determines the differences ofthe amounts of the charges accumulated respectively in the thirdcapacitors and fourth capacitors of second charge accumulation circuits410 and outputs a voltage that is in accordance with the differences.Second difference operational circuit 440 has a composition equivalentto that of first difference operational circuit 340 shown in FIG. 26 andhas a capacitor and an amp disposed in that order between an inputterminal and an output terminal and has a switch and a capacitorconnected in parallel to each other between the input and output of theamp. Second difference operational circuit 440 charges the capacitor,which is cascade-connected with the amp, with just charge Q3 from secondintegrating circuit 430 when the switch is closed, and discharges thecapacitor, connected in parallel to the amp, by just charge Q4 thatflows in via the capacitor, cascade-connected with the amp, from secondintegrating circuit 430 when the switch is opened. The differencebetween charge Q3 and charge Q4, that is, charge (Q3−Q4) is thusaccumulated in the capacitor connected in parallel to the amp and avoltage that is in accordance with the accumulated charge (Q3−Q4) isoutput from the amp. As with the above-described switch SW₄₅, thepresent switch is opened and closed based on the Clamp signal outputfrom timing control circuit 50.

Second A/D conversion circuit 270 successively inputs the voltages(analog values) from second difference operational circuit 440, convertsthese voltages into digital values, and outputs these digital values.The digital values output from second A/D conversion circuit 270 areoutputs that express the luminance profile (digital data) in the firstdirection.

The operations of first signal processing circuit 20 and second signalprocessing circuit 30 of the photodetector of the third embodiment shallnow be described based on FIG. 27. FIG. 27 is a timing chart fordescribing the operations of the first signal processing circuit.

At time t₁, by control signal R becoming “High,” switches SW₄₃ of therespective first charge accumulation circuits 310 close and inputterminal 310A is initialized by being set at first reference potentialV_(ref1). At time t₂, by control signal R becoming “Low,” switches SW₄₃open.

After time t₃, at which point switches SW_(41B) of the respective firstcharge accumulation circuits 310 are closed by control signal B becoming“High,” currents, corresponding to the charges accumulated in the firstgroups of the photosensitive portions 12 _(mn) during the period fromtime t₂ to t₄ (second period), are output until switches SW_(41B) openat time t₄, and charges corresponding to the electric currents areaccumulated in second capacitors C_(41B) of the respective first chargeaccumulation circuits 310. At this time, spot light is not illuminatedfrom light emitting element 5 and the charges accumulated in secondcapacitors C_(41B) are charges corresponding to just the backgroundlight components.

At time t₅, by control signal R becoming “High” again, switches SW₄₃ ofthe respective first charge accumulation circuits 310 close and inputterminal 310A is initialized by being set at first reference potentialV_(ref1). At time t₆, by control signal R becoming “Low,” switches SW₄₃open.

After time t₇, at which point switches SW_(41A) of the respective firstcharge accumulation circuits 310 are closed by control signal A becoming“High,” currents, corresponding to the charges accumulated in the firstgroups of the photosensitive portions 12 _(mn) during the period fromtime t₆ to t₈ (first period), are output until switches SW_(41A) open attime t₈, and charges corresponding to the electric currents areaccumulated in first capacitors C_(41A) of the respective first chargeaccumulation circuits 310. At this time, in the period from t₆ to t₇,spot light is illuminated from light emitting element 5 onto an objectand since both the spot light components reflected from the object andthe background light components are made incident on photosensitiveregion 10, the charges accumulated in first capacitors C_(41A) arecharges corresponding to the background light components and the spotlight components.

At time t₈, by the Reset signal becoming “High,” switch SW₄₄ of firstintegrating circuits 330 closes and capacitor C₄₂ is discharged andthereby initialized. Also, by the Clamp signal becoming “High” as well,switch SW₄₅ of first difference operational circuit 340 closes andaccumulation of charge in (charging of) capacitor C₄₃ is enabled.

At time t₉, by the Reset signal becoming “Low,” switch SW₄₄ of firstintegrating circuit 330 opens. Than at time t₁₀, by signal shift(H_(1B))becoming “High,” switch SW_(42B) of first charge accumulation circuit310 corresponding to the first group of the photosensitive portions 12_(1n) closes and the charges accumulated in second capacitor C_(41B) ofthis first charge accumulation circuit 310 are output as a current. Atfirst integrating circuit 330, into which this electric current isinput, charges are accumulated in capacitor C₄₂ and a voltage V_(out1)that is in accordance with the amount of the accumulated charges isoutput from first integrating circuit 330. This voltage V_(out1) fromfirst integrating circuit 330 is held in capacitor C₄₃ of firstdifference operational circuit 340. Voltage V_(out1), which is outputfrom first integrating circuit 330 at this time, corresponds to just thebackground light component.

At time t₁₁, by signal shift(H_(1B)) becoming “Low,” switch SW_(42B) offirst charge accumulation circuit 310 corresponding to the first groupof the photosensitive portions 12 _(1n) opens. Also, by the Clamp signalbecoming “Low,” switch SW₄₅ of first difference operational circuit 340opens and discharge by just the amount of charges flowing into capacitorC₄₄ is enabled.

At time t₁₂, by signal shift(H_(1A)) becoming “High,” switch SW_(42A) offirst charge accumulation circuit 310 corresponding to the first groupof the photosensitive portions 12 _(1n) closes and the chargesaccumulated in first capacitor C_(41A) of this first charge accumulationcircuit 310 are output as a current. At first integrating circuit 330,into which this electric current is input, charges are accumulated incapacitor C₄₂ and a voltage V_(out1) that is in accordance with theamount of the accumulated charges is output from first integratingcircuit 330. This voltage V_(out1) from first integrating circuit 330 atthis time corresponds to the background light component and a spot lightcomponent.

Also by switch SW₄₅ of first difference operational circuit 340 beingopened, the difference, between the voltage corresponding to the chargesaccumulated in second capacitor C_(41B) and the voltage corresponding tothe charges accumulated in first capacitor C_(41A), is held in capacitorC₄₄ of first difference operational circuit 340. The voltage that isheld in capacitor C₄₄ of first difference operational circuit 340 isoutput via amp A₄₂. This voltage V_(out2) from amp A₄₂ corresponds tojust the spot light component.

At time t₁₃, by signal shift(H_(1A)) becoming “Low,” switch SW_(42A) offirst charge accumulation circuit 310 corresponding to the first groupof the photosensitive portions 12 _(1n) opens. Also, by the Reset signalbecoming “High,” switch SW₄₄ of first integrating circuit 330 closes andby the Clamp signal also becoming “High,” switch SW₄₅ of firstdifference operational circuit 340 closes.

Subsequently in the period from time t₁₃ to t₁₄, the same processes asthose of the period from time t₈ to t₁₃ are carried out and a voltageV_(out2), corresponding to the first group of the photosensitiveportions 12 _(2n), is output from first difference operational circuit340. Hereinafter, the processes of the period from time t₈ to t₁₃ arecarried out repeatedly so that voltages V_(out2), respectivelycorresponding to the respective first groups of the photosensitiveportions 12 _(mn), are output successively from first differenceoperational circuit 340. As mentioned above, voltages V_(out2) fromfirst difference operational circuit 340 are successively input intofirst A/D conversion circuit 170, converted into digital values, andoutput from first A/D conversion circuit 170.

Second charge accumulation circuits 410, second shift register 420,second integrating circuit 430, second difference operational circuit440, and second A/D conversion circuit 270, included in second signalprocessing circuit 30 perform operations equivalent to those (see FIG.27) of first charge accumulation circuits 310, first shift register 320,first integrating circuit 330, first difference operational circuit 340,and first A/D conversion circuit 170 of first signal processing circuit20 and a voltage, of voltage values corresponding to just the spot lightcomponents, is output from first difference operational circuit 340. Asmentioned above, the voltage from first difference operational circuit340 is successively input into second A/D conversion circuit 270 andconverted into digital values that are output from second A/D conversioncircuit 270.

Thus even with the photodetector of the third embodiment, even whenbackground light is made incident on photosensitive region 10, theluminance profiles in the first and second directions can be detected instates in which the background light components are eliminated. As aresult, the two-dimensional position of the light made incident onphotosensitive region 10 can be detected at extremely high precision.

Also with the photodetector of the third embodiment, first signalprocessing circuit 20 includes first charge accumulation circuits 310,each having first capacitor C_(41A) and second capacitor C_(41B), andfirst difference operational circuit 340, and second signal processingcircuit 30 includes second charge accumulation circuits 410, each havingthe third capacitor and the fourth capacitor, and second differenceoperational circuit 440. Thus in each first charge accumulation circuit310, charges are accumulated in first capacitor C_(41A) in accordancewith electric currents corresponding to charges accumulated in thecorresponding first group of the photosensitive portions 12 _(mn) overthe first period and charges are accumulated in second capacitor C_(41B)in accordance with electric currents corresponding to chargesaccumulated in the corresponding first group of the photosensitiveportions 12 _(mn) over the second period, and in first differenceoperational circuit 340, differences in the amounts of chargesaccumulated respectively in first capacitors C_(41A) and secondcapacitors C_(41B) are determined and a voltage V_(out2) that is inaccordance with these differences is output. Also, in each second chargeaccumulation circuit 410, charges are accumulated in the third capacitorin accordance with electric currents corresponding to chargesaccumulated in the corresponding second group of the photosensitiveportions 13 _(mn) over the first period and charges are accumulated inthe fourth capacitor in accordance with electric currents correspondingto charges accumulated in the corresponding second group of thephotosensitive portions 13 _(mn) over the second period, and in thesecond difference operational circuit, differences in the amounts of thecharges accumulated respectively in the third capacitors and the fourthcapacitors are determined and a voltage that is in accordance with thesedifferences is output. The first and second signal processing circuits20 and 30 can thus be simplified in composition and made low in cost.

First signal processing circuit 20 furthermore comprises firstintegrating circuit 330 and first A/D conversion circuit 170 and secondsignal processing circuit 30 furthermore comprises second integratingcircuit 430 and second A/D conversion circuit 270. Luminance profiles inthe first and second directions can thereby be output as digital values.

Fourth Embodiment

A photodetector of a fourth embodiment shall now be described based onFIG. 28 to FIG. 31. The photodetector of the first embodiment and thephotodetector of the fourth embodiment differ in the compositions offirst signal processing circuit 20 and second signal processing circuit30.

As shown in FIG. 28, first signal processing circuit 20 of thephotodetector of the fourth embodiment comprises first integratingcircuits 510, first eliminating circuits 520, first differenceoperational circuits 530, first S/H circuits 140, a first shift register150, first switches 160, and a first A/D conversion circuit 170. FIG. 28is a schematic composition diagram of the first signal processingcircuit.

First integrating circuits 510 are provided in correspondence to thefirst groups of the photosensitive portions 12 _(mn) and each convertsthe electric currents from a corresponding first group of thephotosensitive portions 12 _(mn) into a voltage and outputs thisvoltage. As shown in FIG. 30, each first integrating circuit 510 isarranged with an amp A₁₁, which amplifies a photocurrent I1 that isinput from the corresponding first group of the photosensitive portions12 _(mn), and a capacitor C₁₁ and a switch SW₁₁, which are connected inparallel between the input and output contacts of amp A₁₁. Thus whenswitch SW₁₁ is put in an OFF state by means of a reset signal RS1,capacitor C₁₁ is charged by photocurrent I1, and when switch SW₁₁ is putin an ON state by means of reset signal RS1, the charges in capacitorC₁₁ are discharged. Here in order to set the integrating operation timeof first integrating circuit 510 to a few μsec, the capacitance ofcapacitor C₁₁ is set to a few pF. Connection of capacitor C₁₁ to theinterval between the input and output terminals of amp A₁₁ is controlledby an “ON/OFF” signal (ST) of a switch SW₁₂.

First eliminating circuits 520 are provided in correspondence to thefirst groups of the photosensitive portions 12 _(mn) and eliminate theelectric currents from the first groups of the photosensitive portions12 _(mn) in the above-mentioned second period from the electric currentsfrom the first groups of the photosensitive portions 12 _(mn) in theabove-mentioned first period and output the elimination results. As alsoshown in FIG. 30, first eliminating circuits 520 are connected to theinput terminals of first integrating circuits 510. Each firsteliminating circuit 520 is equipped with a first MOS transistor MQ₅₁,the source terminal of which is connected to the input terminal of thecorresponding first integrating circuit 510 and the drain terminal ofwhich is connected to GND (ground level), and the gate terminal of firstMOS transistor MQ₅₁ is grounded via a first capacitor C₅₁. To the gateterminal of first MOS transistor MQ₅₁, the output of the correspondingfirst integrating circuit 510 is connected via a first switch SW₅₁, the“ON/OFF” of which is controlled by a control signal RM, issued fromtiming control circuit 50.

First difference operational circuits 530 are provided in correspondenceto first integrating circuits 510 and each holds the voltage, among thevoltages from the corresponding first integrating circuit 510, thatcorresponds to the above-mentioned second period (the voltage (analogvalue) that is in accordance with the electric currents corresponding tothe charges accumulated in corresponding first group of thephotosensitive portions 12 _(mn) over the above-mentioned second period)and outputs a voltage that is in accordance with the difference withrespect to the voltage, among the voltages from the corresponding firstintegrating circuit 510, that corresponds to the above-mentioned firstperiod (the voltage (analog value) that is in accordance with theelectric currents corresponding to the charges accumulated incorresponding first group of the photosensitive portions 12 _(mn) overthe above-mentioned first period). As also shown in FIG. 30, each firstdifference operational circuit 530 is connected to the output contact ofthe corresponding first integrating circuit 510 (that is, the outputcontact of amp A₁₁). First difference operational circuit 530 iscomposed with a switch SW₆₁, a capacitor C₆₁, an amp A₆₁, and acapacitor C₆₂ and a switch SW₆₂, which are connected in parallel betweenthe input and output contacts of the amp. The output contact of amp A₆₁is connected to an output terminal. Due to the relationships between theoperation speed margin and noise margin of the entire circuit,capacitors of equal capacitance value of approximately 1 pF are used ascapacitor C₆₁ and capacitor C₆₂. Furthermore, switch SW₆₁ is switchedbetween the ON state and the OFF state by a switching signal CSW5 outputfrom timing control circuit 50. Also, first difference operationalcircuit 530 performs an accumulation operation when switch SW₆₂ is putin the OFF state by a reset signal RS2 output from timing controlcircuit 50 and stops the accumulation operation when switch SW₆₂ is putin the ON state by reset signal RS2.

As shown in FIG. 29, second signal processing circuit 30 of thephotodetector of the fourth embodiment comprises second integratingcircuits 610, second eliminating circuits 620, second differenceoperational circuits 630, second S/H circuits 240, a second shiftregister 250, second switches 260, and a second A/D conversion circuit270. FIG. 29 is a schematic composition diagram of the second signalprocessing circuit.

Second integrating circuits 610 are provided in correspondence to thesecond groups of the photosensitive portions 13 _(mn) and each convertsthe electric currents from a corresponding second group of thephotosensitive portions 13 _(mn) into a voltage and outputs thisvoltage. Each second integrating circuit 610 has an compositionequivalent to first integrating circuit 510 shown in FIG. 30 and isarranged with an amp, which amplifies a photocurrent that is input fromthe corresponding second group of the photosensitive portions 13 _(mn),and a capacitor and a switch, which are connected in parallel betweenthe input and output contacts of the amp.

Second eliminating circuits 620 are provided in correspondence to thesecond groups of the photosensitive portions 13 _(mn) and eliminate theelectric currents from the second groups of the photosensitive portions13 _(mn) in the above-mentioned second period from the electric currentsfrom the second groups of the photosensitive portions 13 _(mn) in theabove-mentioned first period and output the elimination results. Eachsecond eliminating circuit 620 has an composition equivalent to that offirst eliminating circuit 520 shown in FIG. 30, and is equipped with asecond MOS transistor, the source terminal of which is connected to theinput terminal of the corresponding second integrating circuit 610 andthe drain terminal of which is connected to GND (ground level), and thegate terminal of the second MOS transistor is grounded via a secondcapacitor. To the gate terminal of the second MOS transistor, the outputof the corresponding second integrating circuit 610 is connected via asecond switch, the “ON/OFF” of which is controlled by control signal RM,issued from timing control circuit 50.

Second difference operational circuits 630 are provided incorrespondence to second integrating circuits 610 and each holds thevoltage, among the voltages from the corresponding second integratingcircuit 610, that corresponds to the above-mentioned second period (thevoltage (analog value) that is in accordance with the electric currentscorresponding to the charges accumulated in corresponding second groupof the photosensitive portions 13 _(mn) over the above-mentioned secondperiod) and outputs a voltage that is in accordance with the differencewith respect to the voltage, among the voltages from the correspondingsecond integrating circuit 610, that corresponds to the above-mentionedfirst period (the voltage (analog value) that is in accordance with theelectric currents corresponding to the charges accumulated incorresponding second group of the photosensitive portions 13 _(mn) overthe above-mentioned first period). Each second difference operationalcircuit 630 has a composition that is equivalent to that of firstdifference operational circuit 530 shown in FIG. 30, and is arrangedwith a switch, a capacitor, an amp, and a capacitor and a switch, whichare connected in parallel between the input and output contacts of theamp.

The operations of first signal processing circuit 20 and second signalprocessing circuit 30 of the photodetector of the fourth embodimentshall now be described based on FIG. 31. FIG. 31 is a timing chart fordescribing the operations of the first signal processing circuit.

First, in a stationary background light component detection period T,light emitting element 5 is set to a state of not outputting spot lightand first switches SW₅₁ are turned ON to detect the background light. Atthe same time, each first integrating circuit 510 is set to thenon-integrating operation state by switch SW₁₁ being set to “ON” byreset signal RS1, which is output from timing control circuit 50, andswitch SW₁₂ being set to “OFF” by control signal ST, which is outputfrom timing control circuit 50. In this state, electric currents fromthe first groups of the photosensitive portions 12 _(mn) correspondingto the respective first integrating circuits 510 are input into theinput terminals of the respective first integrating circuits 510. Thenby the voltages from first integrating circuits 510 in thenon-integrating operation state being supplied to the gate terminals offirst MOS transistors MQ₅₁, the currents are eliminated entirely byfirst MOS transistors MQ₅₁ of first eliminating circuits 520. In thisstate, the gate-source voltage Vgs of each first MOS transistor MQ₅₁ isexpressed as follows:Vgs=(2×I _(τ)/β)^(1/2) +Vth   (1)

-   I_(τ): current value-   β: constant determined by the size of first MOS transistor MQ₅₁-   Vth: threshold value of first MOS transistor MQ₅₁

After the elapse of time T, first switch SW₅₁ is set to “OFF.” As aresult, only the current value that was supplied to the input terminalof each first integrating circuit 510 at the point at which first switchSW₅₁ is set to “OFF” continues to flow through first MOS transistorMQ₅₁. That is, gate-source voltage Vgs of first MOS transistor MQ₅₁ isheld and the average contribution of the background light, which is themain noise component in subsequent measurement, is thus eliminated.

Then after setting each switch SW₁₂ to “ON” and setting each firstintegrating circuit 510 to the integrating operation state, switch SW₁₁is set to “OFF” for a background light variation amount detection periodT1 (time width: τ). When this state is set, a electric current,corresponding to the variation amount of the background light, flowsinto each first integrating circuit 510 and charges capacitor C₁₁.

Thus in period T1, since just the background light is made incident anda photocurrent variation amount I1, resulting from the variation of thebackground light, is charged in capacitor C₁₁ of each first integratingcircuit 510, integrating output V1 increases gradually. Then if V11 isthe voltage of the integrating output of a first integrating circuit 510after the elapse of time τ and I_(d) is the current input, according tothe variation amount of the background light, from the correspondingfirst group of the photosensitive portions 12 _(mn), since I1=I_(d),V11=I _(d) ·τ/C11   (2)

-   C11: capacitance of capacitor C₁₁

After the elapse of time τ, the corresponding switch SW₆₁ is set to “ON”momentarily, thereby connecting the corresponding first differenceoperational circuit 530 and voltage V11 is held in capacitor C₆₁. Alsoafter the elapse of time τ, switches SW₁₁ are switched to “ON” and firstintegrating circuits 510 are reset.

Light emitting element 5 is then lit for a (spot light+background lightvariation amount) detection period T2 (time width: τ). At the same timeas this lighting, switches SW₁₁ and SW₆₂ are set to “OFF.” As a resultof these switching operations, each integrating circuit 510 chargescapacitor C₁₁ with photocurrent I1, which corresponds to the sum of thebackground light variation amount and the spot light component.

Here, if V12 is the voltage of the integrating output of a firstintegrating circuit 510 at the point of elapse of time τ, I_(sh) is thecurrent due to the reflected spot light component, and, due to the lightintensity of the variation amount of the background light not changingfrom that of period T1, I_(d) is the current corresponding to thebackground light variation amount, since I1=I_(d)+I_(sh), the followingrelationship holds:V12=(I _(sh) +I _(d))·τ/C11   (3)

After the elapse of the period T2, switch SW₆₁ is set to “ON”momentarily and voltage V12 of the integration output of firstintegrating circuit 510 is transmitted to the corresponding firstdifference operational circuit 530. Since first difference operationalcircuit 530 is in the reset state in period T1 and performs asubtraction operation in period T2, by the principle of chargeconservation, charges that are in accordance with the following are heldin capacitors C₆₁ and C₆₂.(V12−V11)·C12=V _(ol) ·C13   (4)

-   C12 : capacitance of capacitor C₆₁-   C13: capacitance of capacitor C₆₂

Then by substituting Equations (2) and (3) in Equation (4) above, thevoltage of output V_(ol) that is generated at the output terminal offirst difference operational circuit 530 is expressed as follows:V _(ol) =I _(sh) ·τ·C12/C11·C13   (5)Also, if capacitor C₆₁ and capacitor C₆₂ are equal in capacitance:V _(ol) =I _(sh) ·τ/C11   (6)

When switch SW₄ of a first S/H circuit 140 closes, output V_(ol) that isgenerated at the output terminal of the corresponding differenceoperational circuit 530 is held by capacitor C₄ of first S/H circuit 140and is output. The voltages from the respective first S/H circuits 140are successively input into first A/D conversion circuit 170 asdescribed above, converted into digital values, and output from firstA/D conversion circuit 170.

Second integrating circuits 610, second eliminating circuits 620, seconddifference operational circuits 630, second S/H circuits 240, secondshift register 250, second switches 260, and second A/D conversioncircuit 270, included in second signal processing circuit 30, performoperations equivalent to those (see FIG. 31) of first integratingcircuits 510, first eliminating circuits 520, first differenceoperational circuits 530, first S/H circuits 140, first shift register150, first switches 160, and first A/D conversion circuit 170, includedin first signal processing circuit 20, and voltages, having voltagevalues corresponding to just the spot light components, are output fromsecond S/H circuits 240. The voltages from the respective second S/Hcircuits 240 are successively input into second A/D conversion circuit270 as described above, converted into digital values, and output fromsecond A/D conversion circuit 270.

Thus even with the photodetector of the fourth embodiment, even whenbackground light is made incident on photosensitive region 10, theluminance profiles in the first and second directions can be detected instates in which the background light components are eliminated. As aresult, the two-dimensional position of the light made incident onphotosensitive region 10 can be detected at extremely high precision.

Also with the photodetector of the fourth embodiment, by means of firsteliminating circuits 520, the electric currents from the first groups ofthe photosensitive portions 12 _(mn) in the above-mentioned secondperiod are eliminated from the electric currents from the first groupsof the photosensitive portions 12 _(mn) in the above-mentioned firstperiod. Thus even if background light is made incident on photosensitiveregion 10, the luminance profile in the second direction can be detectedwith the background light components being eliminated. Also by means ofsecond eliminating circuits 620, the electric currents from the secondgroups of the photosensitive portions 13 _(mn) in the above-mentionedsecond period are eliminated from the electric currents from the secondgroups of the photosensitive portions 13 _(mn) in the above-mentionedfirst period. Thus even if background light is made incident onphotosensitive region 10, the luminance profile in the first directioncan be detected with the background light components being eliminated.As a result, the two-dimensional position of the incident light can bedetected at extremely high precision.

Also with the photodetector of the fourth embodiment, each firsteliminating circuit 520 is equipped with first MOS transistor MQ₅₁, thesource terminal of which is connected to the correspondingphotosensitive portions 12 _(mn) and the drain terminal of which isgrounded, first capacitor C₅₁, one terminal of which is connected to thegate terminal of first MOS transistor MQ₅₁ and the other terminal ofwhich is grounded, and first switch SW₅₁, one terminal of which isconnected to the gate terminal of first MOS transistor MQ₅₁ and theother terminal of which is connected to the output of the correspondingfirst integrating circuit 510, and each second eliminating circuit 620is equipped with the second MOS transistor, the source terminal of whichis connected to the corresponding photosensitive portions and the drainterminal of which is grounded, the second capacitor, one terminal ofwhich is connected to the gate terminal of the second MOS transistor andthe other terminal of which is grounded, and the second switch, oneterminal of which is connected to the gate terminal of the second MOStransistor and the other terminal of which is connected to the output ofthe corresponding second integrating circuit. The above-described firstand second eliminating circuits 520 and 620 can thus be arranged simplyand at low cost.

Also the photodetector of the fourth embodiment further comprises firstdifference operational circuits 530, first S/H circuits 140, first A/Dconversion circuit 170, second difference operational circuits 630,second S/H circuits 240, and second A/D conversion circuit 270.Background light components can thereby be eliminated definitely toenable the luminance profile in the first direction and the luminanceprofile in the second direction to be obtained at even higher precision.Also, the luminance profiles in the first and second directions can beoutput as digital values.

The present invention is not limited to the above-described embodiments.For example, in place of using shift registers, the respectivephotosensitive portions 12 _(mn) and 13 _(mn) (second conductive typesemiconductor regions 41 and 42) may be connected to wires of uniformresistance, the charges generated in accompaniment with the incidence oflight may be taken out from ends of the resistance wires upon dividingthe resistance so as to be inversely proportional to the distancebetween the position at which charges flow into a resistance wire andthe end of the same resistance wire, and the light incidence positionsmay be determined based on the electric currents of the ends of theresistance wires.

Also though with the above-described embodiment, a single pixel isarranged from a plurality of photosensitive portions, a single pixel maybe arranged from a single photosensitive portion instead. For example asshown in FIG. 32, photosensitive region 10 may be made to comprise aplurality of first photosensitive portions 12 _(mn), which areelectrically connected to each other across the first direction, and aplurality of second photosensitive portions 13 _(mn), which areelectrically connected to each other across the second direction and theplurality of first photosensitive portions 12 _(mn) and the plurality ofsecond photosensitive portions 13 _(mn) may be arrayed in atwo-dimensionally mixed state on the same plane. In this case, firstphotosensitive portions 12 _(mn) and second photosensitive portions 13_(mn) are arrayed in a checkered pattern, and first photosensitiveportions 12 _(mn) and second photosensitive portions 13 _(mn) arealigned alternately in the first direction and the second direction.Also, instead of arraying in a checkered pattern, the photosensitiveportions may be arrayed in a honeycomb-like manner as shown in FIG. 8.

Also, first signal processing circuit 20 and second signal processingcircuit 30 may be made to operate at the same timing or operateindependently in the order of a time sequence.

INDUSTRIAL APPLICABILITY

The present invention's photodetector can be used in a reflected lightor direct light incidence position detection system.

1. A photodetector, having a photosensitive region, in which pixels arearrayed two-dimensionally, and being used with a light source thatilluminates light onto an object, wherein a single pixel is arranged byadjacently positioning on the same plane a plurality of photosensitiveportions, each outputting a current that is in accordance with anintensity of light incident thereon and, in each plurality of pixelsthat are aligned in a first direction of the two-dimensional array, onephotosensitive portion among the plurality of photosensitive portionsmaking up each corresponding pixel is electrically connected to the samephotosensitive portion of each of the other corresponding pixels and, ineach plurality of pixels that are aligned in a second direction of thetwo-dimensional array, another photosensitive portion among theplurality of photosensitive portions making up each corresponding pixelis electrically connected to the same photosensitive portion of each ofthe other corresponding pixels, the photodetector comprising: a firstsignal processing circuit, detecting a luminance profile in the seconddirection based on differences between outputs, corresponding to chargesaccumulated in first groups of the photosensitive portions that areelectrically connected across the pluralities of pixels aligned in thefirst direction over a first period wherein the light is illuminatedonto the object by the light source, and outputs, corresponding tocharges accumulated in the first groups of the photosensitive portionsover a second period wherein the light is not illuminated onto theobject by the light source; and a second signal processing circuit,detecting a luminance profile in the first direction based ondifferences between outputs, corresponding to charges accumulated insecond groups of the photosensitive portions that are electricallyconnected across the pluralities of pixels aligned in the seconddirection over the first period, and outputs, corresponding to chargesaccumulated in the second groups of the photosensitive portions over thesecond period.
 2. The photodetector according to claim 1, wherein thefirst signal processing circuit comprises: a first shift register forsuccessively reading, in the second direction, the electric currentsfrom the first groups of the photosensitive portions a first integratingcircuit, successively inputting the electric currents from therespective first groups of the photosensitive portions that are readsuccessively by the first shift register and converting and outputtingthe electric currents into and as a voltage; a first CDS circuit,outputting a voltage corresponding to the variation amount of thevoltage from the first integrating circuit; a first A/D conversioncircuit, converting the voltage from the first CDS circuit into digitalvalues and outputting the digital values; and a first differenceoperational circuit, determining, based on the digital values outputfrom the first A/D conversion circuit, differences between digitalvalues corresponding to the first period and digital valuescorresponding to the second period; and the second signal processingcircuit comprises: a second shift register for successively reading, inthe first direction, the electric currents from the second groups of thephotosensitive portions; a second integrating circuit, successivelyinputting the electric currents from the respective second groups of thephotosensitive portions that are read successively by the second shiftregister and converting and outputting the electric currents into and asa voltage; a second CDS circuit, outputting a voltage corresponding tothe variation amount of the voltage from the second integrating circuit;a second A/D conversion circuit, converting the voltage from the secondCDS circuit into digital values and outputting the digital values; and asecond difference operational circuit, determining, based on the digitalvalues output from the second A/D conversion circuit, differencesbetween digital values corresponding to the first period and digitalvalues corresponding to the second period.
 3. The photodetectoraccording to claim 2, wherein the first signal processing circuitfurther comprises: a first digital memory, disposed between the firstA/D conversion circuit and the first difference operational circuit andstoring the digital values corresponding to the first period and thedigital values corresponding to the second period and outputting thestored digital values to the first difference operational circuit; andthe second signal processing circuit further comprises: a second digitalmemory, disposed between the second A/D conversion circuit and thesecond difference operational circuit and storing the digital valuescorresponding to the first period and the digital values correspondingto the second period and outputting the stored digital values to thesecond difference operational circuit.
 4. The photodetector according toclaim 1, wherein the first signal processing circuit comprises: firstintegration circuits, provided in correspondence to the first groups ofthe photosensitive portions and each converting and outputting theelectric currents from the corresponding first group of thephotosensitive portions into and as a voltage; first CDS circuits,disposed in correspondence to the first integration circuits and each inturn comprising a first coupling capacitance element and a firstamplifier, disposed in that order between an output terminal and aninput terminal that inputs the voltage from the corresponding firstintegration circuit, a first integrating capacitance element, disposedin parallel between the input and the output of the first amplifier, anda first switching element, making charges of an amount corresponding tothe variation amount of the voltage be accumulated in the firstintegrating capacitance element; second CDS circuits, disposed incorrespondence to the first integration circuits and each in turncomprising a second coupling capacitance element and a second amplifier,disposed in that order between an output terminal and an input terminalthat inputs the voltage from the corresponding first integrationcircuit, a second integrating capacitance element, having a capacitancevalue equal to the capacitance value of the first integratingcapacitance element and disposed in parallel between the input and theoutput of the second amplifier, and a second switching element, makingcharges of an amount corresponding to the variation amount of thevoltage be accumulated in the second integrating capacitance element;and first difference operational circuits, disposed in correspondence tothe first CDS circuits and the second CDS circuits and each determininga difference in the amounts of charges respectively accumulated in thefirst integrating capacitance element of the corresponding first CDScircuit and the second integrating capacitance element of thecorresponding second CDS circuit and outputting a voltage that is inaccordance with the difference; and the second signal processing circuitcomprises: second integration circuits, provided in correspondence tothe second groups of the photosensitive portions and each converting andoutputting the electric currents from the second corresponding group ofthe photosensitive portions as a voltage; third CDS circuits, disposedin correspondence to the second integration circuits and each in turncomprising a third coupling capacitance element and a third amplifier,disposed in that order between an output terminal and an input terminalthat inputs the voltage from the corresponding second integrationcircuit, a third integrating capacitance element, disposed in parallelbetween the input and the output of the third amplifier, and a thirdswitching element, making charges of an amount corresponding to thevariation amount of the voltage be accumulated in the third integratingcapacitance element; fourth CDS circuits, disposed in correspondence tothe second integration circuit and each in turn comprising a fourthcoupling capacitance element and a fourth amplifier, disposed in thatorder between an output terminal and an input terminal that inputs thevoltage from the corresponding second integration circuit, a fourthintegrating capacitance element, having a capacitance value equal to thecapacitance value of the third integrating capacitance element anddisposed in parallel between the input and the output of the fourthamplifier, and a fourth switching element, making charges of an amountcorresponding to the variation amount of the voltage be accumulated inthe fourth integrating capacitance element; and second differenceoperational circuits, disposed in correspondence to the third CDScircuits and the fourth CDS circuits and each determining a differencein the amounts of charges respectively accumulated in the thirdintegrating capacitance element of the corresponding third CDS circuitand the fourth integrating capacitance element of the correspondingfourth CDS circuit and outputting a voltage that is in accordance withthe difference.
 5. The photodetector according to claim 4, wherein thefirst signal processing circuit further comprises: first sample-and-holdcircuits, provided in correspondence to the first difference operationalcircuits and each holding and then outputting the voltage from thecorresponding first difference operational circuit; and a first A/Dconversion circuit, successively inputting the voltages from therespective first sample-and-hold circuits, converting the voltages intodigital values, and outputting the digital values; and the second signalprocessing circuit further comprises: second sample-and-hold circuits,provided in correspondence to the second difference operational circuitsand each holding and then outputting the voltage from the correspondingsecond difference operational circuit; and a second A/D conversioncircuit, successively inputting the voltage from the respective secondsample-and-hold circuits, converting the voltage into digital values,and outputting the digital values.
 6. The photodetector according toclaim 1, wherein the first signal processing circuit comprises: firstcharge accumulation circuits, provided in correspondence to therespective first groups of the photosensitive portions and eachcomprising a first capacitance element and a second capacitance element,disposed in parallel between an output terminal and an input terminalthat inputs the electric currents from the corresponding first group ofthe photosensitive portions, and accumulating charges in the firstcapacitance element in accordance with the electric currentscorresponding to the charges accumulated during the first period in thecorresponding first group of the photosensitive portions andaccumulating charges in the second capacitance element in accordancewith the electric currents corresponding to the charges accumulatedduring the second period in the corresponding first group of thephotosensitive portions; and a first difference operational circuit,determining the differences between the charge amounts accumulatedrespectively in the first capacitance elements and the secondcapacitance elements of the first charge accumulation circuits andoutputting a voltage that is in accordance with the differences; and thesecond signal processing circuit comprises: second charge accumulationcircuits, provided in correspondence to the respective second groups ofthe photosensitive portions and each comprising a third capacitanceelement and a fourth capacitance element, disposed in parallel betweenan output terminal and an input terminal that inputs the electriccurrents from the corresponding second group of the photosensitiveportions, and accumulating charges in the third capacitance element inaccordance with the electric currents corresponding to the chargesaccumulated during the first period in the corresponding second group ofthe photosensitive portions and accumulating charges in the fourthcapacitance element in accordance with the electric currentscorresponding to the charges accumulated during the second period in thecorresponding second group of the photosensitive portions; and a seconddifference operational circuit, determining the differences between thecharge amounts accumulated respectively in the third capacitanceelements and the fourth capacitance elements of the second chargeaccumulation circuits and outputting a voltage that is in accordancewith the differences.
 7. The photodetector according to claim 6, whereinthe first signal processing circuit furthermore comprises: a firstintegrating circuit, successively inputting, from the first capacitanceelements and the second capacitance elements, electric currentscorresponding to the charges accumulated in the corresponding firstcapacitance elements and second capacitance elements and converting theelectric currents into a voltage and outputting the voltage to the firstdifference operational circuit; and a first A/D conversion circuit,successively inputting the voltage from the first difference operationalcircuit, converting the voltage into digital values, and outputting thedigital values; and the second signal processing circuit furthermorecomprises: a second integrating circuit, successively inputting, fromthe third capacitance elements and the fourth capacitance elements,electric currents corresponding to the charges accumulated in thecorresponding third capacitance elements and fourth capacitance elementsand converting the electric currents into a voltage and outputting thevoltage to the second difference operational circuit; and a second A/Dconversion circuit, successively inputting the voltage from the seconddifference operational circuit, converting the voltage into digitalvalues, and outputting the digital values.
 8. A photodetector, having aphotosensitive region, in which pixels are arrayed two-dimensionally,and being used with a light source that illuminates light onto anobject, wherein a single pixel is arranged by adjacently positioning onthe same plane a plurality of photosensitive portions, each outputting acurrent that is in accordance with an intensity of light incidentthereon and, in each plurality of pixels that are aligned in a firstdirection of the two-dimensional array, one photosensitive portion amongthe plurality of photosensitive portions making up each correspondingpixel is electrically connected to the same photosensitive portion ofeach of the other corresponding pixels and, in each plurality of pixelsthat are aligned in a second direction of the two-dimensional array,another photosensitive portion among the plurality of photosensitiveportions making up each corresponding pixel is electrically connected tothe same photosensitive portion of each of the other correspondingpixels, the photodetector comprising: first eliminating circuits, beingprovided in correspondence to the respective first groups of thephotosensitive portions, which are electrically connected across eachthe plurality of pixels aligned in the first direction, and eacheliminating a electric current, which is output from the correspondingfirst group of the photosensitive portions in a second period whereinthe light is not illuminated onto the object by the light source, from aelectric current, which is output from the corresponding first group ofthe photosensitive portions in a first period wherein the light isilluminated onto the object by the light source, and outputting theelectric current resulting from the elimination; first integratingcircuits, being provided in correspondence to the first eliminatingcircuits and each accumulating charges in accordance with the electriccurrent from the corresponding first eliminating circuit and outputtinga voltage that is in accordance with the amount of the accumulatedcharges; second eliminating circuits, being provided in correspondenceto the respective second groups of the photosensitive portions, whichare electrically connected across each the plurality of pixels alignedin the second direction, and each eliminating a electric current, whichis output from the corresponding second group of the photosensitiveportions in the second period, from a electric current, which is outputfrom the corresponding second group of the photosensitive portions inthe first period, and outputting the electric current resulting from theelimination; and second integrating circuits, being provided incorrespondence to the second eliminating circuits and each accumulatingcharges in accordance with the electric current from the correspondingsecond eliminating circuit and outputting a voltage that is inaccordance with the amount of the accumulated charges.
 9. Thephotodetector according to claim 8, wherein each of the firsteliminating circuit comprises: a first MOS transistor, having a sourceterminal connected to the corresponding first group of thephotosensitive portions and a drain terminal that is grounded; a firstcapacitance element, having one terminal connected to a gate terminal ofthe first MOS transistor and another terminal that is grounded; and afirst switching element, having one terminal connected to the gateterminal of the first MOS transistor and another terminal connected tothe output of the corresponding first integrating circuit; and eachsecond eliminating circuit comprises: a second MOS transistor, having asource terminal connected to the corresponding second group of thephotosensitive portions and a drain terminal that is grounded; a secondcapacitance element, having one terminal connected to a gate terminal ofthe second MOS transistor and another terminal that is grounded; and asecond switching element, having one terminal connected to the gateterminal of the second MOS transistor and another terminal connected tothe output of the corresponding second integrating circuit.
 10. Thephotodetector according to claim 8, further comprising: first differenceoperational circuits, provided in correspondence to the firstintegrating circuits and each holding, from among the voltages from thecorresponding first integrating circuit, the voltage corresponding tothe second period and outputting a voltage that is in accordance withthe difference with respect to the voltage, which, among the voltagesfrom the corresponding first integrating circuit, corresponds to thefirst period; first sample-and-hold circuits, provided in correspondenceto the first difference operational circuits and each holding andoutputting the voltage from the corresponding first differenceoperational circuit; a first A/D conversion circuit, successivelyinputting the voltages from the respective first sample-and-holdcircuits, converting the voltages into digital values, and outputtingthe digital values; second difference operational circuits, provided incorrespondence to the second integrating circuits and each holding, fromamong the voltages from the corresponding second integrating circuit,the voltage corresponding to the second period and outputting a voltagethat is in accordance with the difference with respect to the voltage,which, among the voltages from the corresponding second integratingcircuit, corresponds to the first period; second sample-and-holdcircuits, provided in correspondence to the second differenceoperational circuits and each holding and then outputting the voltagefrom the corresponding second difference operational circuit; and asecond A/D conversion circuit, successively inputting the voltages fromthe respective second sample-and-hold circuits, converting the voltagesinto digital values, and outputting the digital values.